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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 45b7a9fc08778b7063ce50301d3ccdd8a7c2a9b5 / . / arch / arm / dts / k3-am64-main.dtsi
blob: 4b6cd6cc9041ba545b4c27305cb6a30d1d00a7b9 [file] [log] [blame]
Dave Gerlach58211db2021-04-23 11:27:44 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM642 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_main {
9 oc_sram: sram@70000000 {
10 compatible = "mmio-sram";
11 reg = <0x00 0x70000000 0x00 0x200000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x00 0x70000000 0x200000>;
15
16 atf-sram@0 {
17 reg = <0x0 0x1a000>;
18 };
19 };
20
21 gic500: interrupt-controller@1800000 {
22 compatible = "arm,gic-v3";
23 #address-cells = <2>;
24 #size-cells = <2>;
25 ranges;
26 #interrupt-cells = <3>;
27 interrupt-controller;
28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
29 <0x00 0x01840000 0x00 0xC0000>; /* GICR */
30 /*
31 * vcpumntirq:
32 * virtual CPU interface maintenance interrupt
33 */
34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
35
36 gic_its: msi-controller@1820000 {
37 compatible = "arm,gic-v3-its";
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
40 msi-controller;
41 #msi-cells = <1>;
42 };
43 };
44
45 dmss: dmss {
46 compatible = "simple-mfd";
47 #address-cells = <2>;
48 #size-cells = <2>;
49 dma-ranges;
50 ranges;
51
52 ti,sci-dev-id = <25>;
53
54 secure_proxy_main: mailbox@4d000000 {
55 compatible = "ti,am654-secure-proxy";
56 #mbox-cells = <1>;
57 reg-names = "target_data", "rt", "scfg";
58 reg = <0x00 0x4d000000 0x00 0x80000>,
59 <0x00 0x4a600000 0x00 0x80000>,
60 <0x00 0x4a400000 0x00 0x80000>;
61 interrupt-names = "rx_012";
62 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
63 };
64
65 inta_main_dmss: interrupt-controller@48000000 {
66 compatible = "ti,sci-inta";
67 reg = <0x00 0x48000000 0x00 0x100000>;
68 #interrupt-cells = <0>;
69 interrupt-controller;
70 interrupt-parent = <&gic500>;
71 msi-controller;
72 ti,sci = <&dmsc>;
73 ti,sci-dev-id = <28>;
74 ti,interrupt-ranges = <4 68 36>;
75 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
76 };
77
78 main_bcdma: dma-controller@485c0100 {
79 compatible = "ti,am64-dmss-bcdma";
80 reg = <0x00 0x485c0100 0x00 0x100>,
81 <0x00 0x4c000000 0x00 0x20000>,
82 <0x00 0x4a820000 0x00 0x20000>,
83 <0x00 0x4aa40000 0x00 0x20000>,
84 <0x00 0x4bc00000 0x00 0x100000>;
85 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
86 msi-parent = <&inta_main_dmss>;
87 #dma-cells = <3>;
88
89 ti,sci = <&dmsc>;
90 ti,sci-dev-id = <26>;
91 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
92 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
93 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
94 };
95
96 main_pktdma: dma-controller@485c0000 {
97 compatible = "ti,am64-dmss-pktdma";
98 reg = <0x00 0x485c0000 0x00 0x100>,
99 <0x00 0x4a800000 0x00 0x20000>,
100 <0x00 0x4aa00000 0x00 0x40000>,
101 <0x00 0x4b800000 0x00 0x400000>;
102 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
103 msi-parent = <&inta_main_dmss>;
104 #dma-cells = <2>;
105
106 ti,sci = <&dmsc>;
107 ti,sci-dev-id = <30>;
108 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
109 <0x24>, /* CPSW_TX_CHAN */
110 <0x25>, /* SAUL_TX_0_CHAN */
111 <0x26>, /* SAUL_TX_1_CHAN */
112 <0x27>, /* ICSSG_0_TX_CHAN */
113 <0x28>; /* ICSSG_1_TX_CHAN */
114 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
115 <0x11>, /* RING_CPSW_TX_CHAN */
116 <0x12>, /* RING_SAUL_TX_0_CHAN */
117 <0x13>, /* RING_SAUL_TX_1_CHAN */
118 <0x14>, /* RING_ICSSG_0_TX_CHAN */
119 <0x15>; /* RING_ICSSG_1_TX_CHAN */
120 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
121 <0x2b>, /* CPSW_RX_CHAN */
122 <0x2d>, /* SAUL_RX_0_CHAN */
123 <0x2f>, /* SAUL_RX_1_CHAN */
124 <0x31>, /* SAUL_RX_2_CHAN */
125 <0x33>, /* SAUL_RX_3_CHAN */
126 <0x35>, /* ICSSG_0_RX_CHAN */
127 <0x37>; /* ICSSG_1_RX_CHAN */
128 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
129 <0x2c>, /* FLOW_CPSW_RX_CHAN */
130 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
131 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
132 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
133 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
134 };
135 };
136
137 dmsc: dmsc@44043000 {
138 compatible = "ti,k2g-sci";
139 ti,host-id = <12>;
140 mbox-names = "rx", "tx";
141 mboxes= <&secure_proxy_main 12>,
142 <&secure_proxy_main 13>;
143 reg-names = "debug_messages";
144 reg = <0x00 0x44043000 0x00 0xfe0>;
145
146 k3_pds: power-controller {
147 compatible = "ti,sci-pm-domain";
148 #power-domain-cells = <2>;
149 };
150
151 k3_clks: clocks {
152 compatible = "ti,k2g-sci-clk";
153 #clock-cells = <2>;
154 };
155
156 k3_reset: reset-controller {
157 compatible = "ti,sci-reset";
158 #reset-cells = <2>;
159 };
160 };
161
162 main_pmx0: pinctrl@f4000 {
163 compatible = "pinctrl-single";
164 reg = <0x00 0xf4000 0x00 0x2d0>;
165 #pinctrl-cells = <1>;
166 pinctrl-single,register-width = <32>;
167 pinctrl-single,function-mask = <0xffffffff>;
168 };
169
170 main_conf: syscon@43000000 {
171 compatible = "syscon", "simple-mfd";
172 reg = <0x00 0x43000000 0x00 0x20000>;
173 #address-cells = <1>;
174 #size-cells = <1>;
175 ranges = <0x00 0x00 0x43000000 0x20000>;
176
177 chipid@14 {
178 compatible = "ti,am654-chipid";
179 reg = <0x00000014 0x4>;
180 };
181 };
182
183 main_uart0: serial@2800000 {
184 compatible = "ti,am64-uart", "ti,am654-uart";
185 reg = <0x00 0x02800000 0x00 0x100>;
186 reg-shift = <2>;
187 reg-io-width = <4>;
188 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
189 clock-frequency = <48000000>;
190 current-speed = <115200>;
191 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
192 clocks = <&k3_clks 146 0>;
193 clock-names = "fclk";
194 };
195
196 main_uart1: serial@2810000 {
197 compatible = "ti,am64-uart", "ti,am654-uart";
198 reg = <0x00 0x02810000 0x00 0x100>;
199 reg-shift = <2>;
200 reg-io-width = <4>;
201 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
202 clock-frequency = <48000000>;
203 current-speed = <115200>;
204 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
205 clocks = <&k3_clks 152 0>;
206 clock-names = "fclk";
207 };
208
209 main_uart2: serial@2820000 {
210 compatible = "ti,am64-uart", "ti,am654-uart";
211 reg = <0x00 0x02820000 0x00 0x100>;
212 reg-shift = <2>;
213 reg-io-width = <4>;
214 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
215 clock-frequency = <48000000>;
216 current-speed = <115200>;
217 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
218 clocks = <&k3_clks 153 0>;
219 clock-names = "fclk";
220 };
221
222 main_uart3: serial@2830000 {
223 compatible = "ti,am64-uart", "ti,am654-uart";
224 reg = <0x00 0x02830000 0x00 0x100>;
225 reg-shift = <2>;
226 reg-io-width = <4>;
227 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
228 clock-frequency = <48000000>;
229 current-speed = <115200>;
230 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
231 clocks = <&k3_clks 154 0>;
232 clock-names = "fclk";
233 };
234
235 main_uart4: serial@2840000 {
236 compatible = "ti,am64-uart", "ti,am654-uart";
237 reg = <0x00 0x02840000 0x00 0x100>;
238 reg-shift = <2>;
239 reg-io-width = <4>;
240 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
241 clock-frequency = <48000000>;
242 current-speed = <115200>;
243 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
244 clocks = <&k3_clks 155 0>;
245 clock-names = "fclk";
246 };
247
248 main_uart5: serial@2850000 {
249 compatible = "ti,am64-uart", "ti,am654-uart";
250 reg = <0x00 0x02850000 0x00 0x100>;
251 reg-shift = <2>;
252 reg-io-width = <4>;
253 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
254 clock-frequency = <48000000>;
255 current-speed = <115200>;
256 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
257 clocks = <&k3_clks 156 0>;
258 clock-names = "fclk";
259 };
260
261 main_uart6: serial@2860000 {
262 compatible = "ti,am64-uart", "ti,am654-uart";
263 reg = <0x00 0x02860000 0x00 0x100>;
264 reg-shift = <2>;
265 reg-io-width = <4>;
266 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
267 clock-frequency = <48000000>;
268 current-speed = <115200>;
269 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
270 clocks = <&k3_clks 158 0>;
271 clock-names = "fclk";
272 };
273
274 main_i2c0: i2c@20000000 {
275 compatible = "ti,am64-i2c", "ti,omap4-i2c";
276 reg = <0x00 0x20000000 0x00 0x100>;
277 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
278 #address-cells = <1>;
279 #size-cells = <0>;
280 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
281 clocks = <&k3_clks 102 2>;
282 clock-names = "fck";
283 };
284
285 main_i2c1: i2c@20010000 {
286 compatible = "ti,am64-i2c", "ti,omap4-i2c";
287 reg = <0x00 0x20010000 0x00 0x100>;
288 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
292 clocks = <&k3_clks 103 2>;
293 clock-names = "fck";
294 };
295
296 main_i2c2: i2c@20020000 {
297 compatible = "ti,am64-i2c", "ti,omap4-i2c";
298 reg = <0x00 0x20020000 0x00 0x100>;
299 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
303 clocks = <&k3_clks 104 2>;
304 clock-names = "fck";
305 };
306
307 main_i2c3: i2c@20030000 {
308 compatible = "ti,am64-i2c", "ti,omap4-i2c";
309 reg = <0x00 0x20030000 0x00 0x100>;
310 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
314 clocks = <&k3_clks 105 2>;
315 clock-names = "fck";
316 };
317
318 main_spi0: spi@20100000 {
319 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
320 reg = <0x00 0x20100000 0x00 0x400>;
321 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
325 clocks = <&k3_clks 141 0>;
326 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
327 dma-names = "tx0", "rx0";
328 };
329
330 main_spi1: spi@20110000 {
331 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
332 reg = <0x00 0x20110000 0x00 0x400>;
333 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
334 #address-cells = <1>;
335 #size-cells = <0>;
336 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
337 clocks = <&k3_clks 142 0>;
338 };
339
340 main_spi2: spi@20120000 {
341 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
342 reg = <0x00 0x20120000 0x00 0x400>;
343 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
347 clocks = <&k3_clks 143 0>;
348 };
349
350 main_spi3: spi@20130000 {
351 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
352 reg = <0x00 0x20130000 0x00 0x400>;
353 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
357 clocks = <&k3_clks 144 0>;
358 };
359
360 main_spi4: spi@20140000 {
361 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
362 reg = <0x00 0x20140000 0x00 0x400>;
363 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
365 #size-cells = <0>;
366 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
367 clocks = <&k3_clks 145 0>;
368 };
369
370 sdhci0: mmc@fa10000 {
371 compatible = "ti,am64-sdhci-8bit";
372 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
373 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
374 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
375 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
376 clock-names = "clk_ahb", "clk_xin";
377 mmc-ddr-1_8v;
378 mmc-hs200-1_8v;
379 mmc-hs400-1_8v;
380 ti,trm-icp = <0x2>;
381 ti,otap-del-sel-legacy = <0x0>;
382 ti,otap-del-sel-mmc-hs = <0x0>;
383 ti,otap-del-sel-ddr52 = <0x6>;
384 ti,otap-del-sel-hs200 = <0x7>;
385 ti,otap-del-sel-hs400 = <0x4>;
386 };
387
388 sdhci1: mmc@fa00000 {
389 compatible = "ti,am64-sdhci-4bit";
390 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
391 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
392 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
393 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
394 clock-names = "clk_ahb", "clk_xin";
395 ti,trm-icp = <0x2>;
396 ti,otap-del-sel-legacy = <0x0>;
397 ti,otap-del-sel-sd-hs = <0xf>;
398 ti,otap-del-sel-sdr12 = <0xf>;
399 ti,otap-del-sel-sdr25 = <0xf>;
400 ti,otap-del-sel-sdr50 = <0xc>;
401 ti,otap-del-sel-sdr104 = <0x6>;
402 ti,otap-del-sel-ddr50 = <0x9>;
403 ti,clkbuf-sel = <0x7>;
404 };
Nishanth Menond3fd37b2021-05-04 18:00:54 -0500[diff] [blame]405
406 main_gpio0: gpio@600000 {
407 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
408 reg = <0x00 0x00600000 0x00 0x100>;
409 gpio-controller;
410 #gpio-cells = <2>;
411 interrupts = <77 0 IRQ_TYPE_EDGE_RISING>,
412 <77 1 IRQ_TYPE_EDGE_RISING>,
413 <77 2 IRQ_TYPE_EDGE_RISING>,
414 <77 3 IRQ_TYPE_EDGE_RISING>,
415 <77 4 IRQ_TYPE_EDGE_RISING>,
416 <77 5 IRQ_TYPE_EDGE_RISING>,
417 <77 6 IRQ_TYPE_EDGE_RISING>,
418 <77 7 IRQ_TYPE_EDGE_RISING>;
419 interrupt-controller;
420 #interrupt-cells = <2>;
421 ti,ngpio = <69>;
422 ti,davinci-gpio-unbanked = <0>;
423 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
424 clocks = <&k3_clks 77 0>;
425 clock-names = "gpio";
426 };
427
428 main_gpio1: gpio@601000 {
429 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
430 reg = <0x00 0x00601000 0x00 0x100>;
431 gpio-controller;
432 #gpio-cells = <2>;
433 interrupts = <78 0 IRQ_TYPE_EDGE_RISING>,
434 <78 1 IRQ_TYPE_EDGE_RISING>,
435 <78 2 IRQ_TYPE_EDGE_RISING>,
436 <78 3 IRQ_TYPE_EDGE_RISING>,
437 <78 4 IRQ_TYPE_EDGE_RISING>,
438 <78 5 IRQ_TYPE_EDGE_RISING>,
439 <78 6 IRQ_TYPE_EDGE_RISING>,
440 <78 7 IRQ_TYPE_EDGE_RISING>;
441 interrupt-controller;
442 #interrupt-cells = <2>;
443 ti,ngpio = <69>;
444 ti,davinci-gpio-unbanked = <0>;
445 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
446 clocks = <&k3_clks 78 0>;
447 clock-names = "gpio";
448 };
Lokesh Vutla45b7a9f2021-05-06 16:44:58 +0530[diff] [blame^]449
450 main_i2c0: i2c@20000000 {
451 compatible = "ti,am64-i2c", "ti,omap4-i2c";
452 reg = <0x0 0x20000000 0x0 0x100>;
453 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 clock-names = "fck";
457 clocks = <&k3_clks 102 2>;
458 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
459 };
460
461 main_i2c1: i2c@20010000 {
462 compatible = "ti,am64-i2c", "ti,omap4-i2c";
463 reg = <0x0 0x20010000 0x0 0x100>;
464 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
465 #address-cells = <1>;
466 #size-cells = <0>;
467 clock-names = "fck";
468 clocks = <&k3_clks 103 2>;
469 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
470 };
471
472 main_i2c2: i2c@20020000 {
473 compatible = "ti,am64-i2c", "ti,omap4-i2c";
474 reg = <0x00 0x20020000 0x0 0x100>;
475 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
477 #size-cells = <0>;
478 clock-names = "fck";
479 clocks = <&k3_clks 104 2>;
480 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
481 };
482
483 main_i2c3: i2c@20030000 {
484 compatible = "ti,am64-i2c", "ti,omap4-i2c";
485 reg = <0x00 0x20030000 0x0 0x100>;
486 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
487 #address-cells = <1>;
488 #size-cells = <0>;
489 clock-names = "fck";
490 clocks = <&k3_clks 105 2>;
491 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
492 };
Dave Gerlach58211db2021-04-23 11:27:44 -0500[diff] [blame]493};