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Robin Getzf19fd872009-12-21 16:35:48 -05001/* Blackfin KGDB header
2 *
3 * Copyright 2005-2009 Analog Devices Inc.
4 *
5 * Licensed under the GPL-2 or later.
6 */
7
8#ifndef __ASM_BLACKFIN_KGDB_H__
9#define __ASM_BLACKFIN_KGDB_H__
10
11/* gdb locks */
12#define KGDB_MAX_NO_CPUS 8
13
14/*
15 * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
16 * At least NUMREGBYTES*2 are needed for register packets.
17 * Longer buffer is needed to list all threads.
18 */
19#define BUFMAX 2048
20
21enum regnames {
22 /* Core Registers */
23 BFIN_R0 = 0,
24 BFIN_R1,
25 BFIN_R2,
26 BFIN_R3,
27 BFIN_R4,
28 BFIN_R5,
29 BFIN_R6,
30 BFIN_R7,
31 BFIN_P0,
32 BFIN_P1,
33 BFIN_P2,
34 BFIN_P3,
35 BFIN_P4,
36 BFIN_P5,
37 BFIN_SP,
38 BFIN_FP,
39 BFIN_I0,
40 BFIN_I1,
41 BFIN_I2,
42 BFIN_I3,
43 BFIN_M0,
44 BFIN_M1,
45 BFIN_M2,
46 BFIN_M3,
47 BFIN_B0,
48 BFIN_B1,
49 BFIN_B2,
50 BFIN_B3,
51 BFIN_L0,
52 BFIN_L1,
53 BFIN_L2,
54 BFIN_L3,
55 BFIN_A0_DOT_X,
56 BFIN_A0_DOT_W,
57 BFIN_A1_DOT_X,
58 BFIN_A1_DOT_W,
59 BFIN_ASTAT,
60 BFIN_RETS,
61 BFIN_LC0,
62 BFIN_LT0,
63 BFIN_LB0,
64 BFIN_LC1,
65 BFIN_LT1,
66 BFIN_LB1,
67 BFIN_CYCLES,
68 BFIN_CYCLES2,
69 BFIN_USP,
70 BFIN_SEQSTAT,
71 BFIN_SYSCFG,
72 BFIN_RETI,
73 BFIN_RETX,
74 BFIN_RETN,
75 BFIN_RETE,
76
77 /* Pseudo Registers */
78 BFIN_PC,
79 BFIN_CC,
80 BFIN_EXTRA1, /* Address of .text section. */
81 BFIN_EXTRA2, /* Address of .data section. */
82 BFIN_EXTRA3, /* Address of .bss section. */
83 BFIN_FDPIC_EXEC,
84 BFIN_FDPIC_INTERP,
85
86 /* MMRs */
87 BFIN_IPEND,
88
89 /* LAST ENTRY SHOULD NOT BE CHANGED. */
90 BFIN_NUM_REGS /* The number of all registers. */
91};
92
93/* Number of bytes of registers. */
94#define NUMREGBYTES (BFIN_NUM_REGS * 4)
95
96static inline void arch_kgdb_breakpoint(void)
97{
98 asm volatile ("EXCPT 2;");
99}
100#define BREAK_INSTR_SIZE 2
101#define CACHE_FLUSH_IS_SAFE 1
102#define GDB_ADJUSTS_BREAK_OFFSET
103#define GDB_SKIP_HW_WATCH_TEST
104#define HW_INST_WATCHPOINT_NUM 6
105#define HW_WATCHPOINT_NUM 8
106#define TYPE_INST_WATCHPOINT 0
107#define TYPE_DATA_WATCHPOINT 1
108
109/* Instruction watchpoint address control register bits mask */
110#define WPPWR 0x1
111#define WPIREN01 0x2
112#define WPIRINV01 0x4
113#define WPIAEN0 0x8
114#define WPIAEN1 0x10
115#define WPICNTEN0 0x20
116#define WPICNTEN1 0x40
117#define EMUSW0 0x80
118#define EMUSW1 0x100
119#define WPIREN23 0x200
120#define WPIRINV23 0x400
121#define WPIAEN2 0x800
122#define WPIAEN3 0x1000
123#define WPICNTEN2 0x2000
124#define WPICNTEN3 0x4000
125#define EMUSW2 0x8000
126#define EMUSW3 0x10000
127#define WPIREN45 0x20000
128#define WPIRINV45 0x40000
129#define WPIAEN4 0x80000
130#define WPIAEN5 0x100000
131#define WPICNTEN4 0x200000
132#define WPICNTEN5 0x400000
133#define EMUSW4 0x800000
134#define EMUSW5 0x1000000
135#define WPAND 0x2000000
136
137/* Data watchpoint address control register bits mask */
138#define WPDREN01 0x1
139#define WPDRINV01 0x2
140#define WPDAEN0 0x4
141#define WPDAEN1 0x8
142#define WPDCNTEN0 0x10
143#define WPDCNTEN1 0x20
144
145#define WPDSRC0 0xc0
146#define WPDACC0_OFFSET 8
147#define WPDSRC1 0xc00
148#define WPDACC1_OFFSET 12
149
150/* Watchpoint status register bits mask */
151#define STATIA0 0x1
152#define STATIA1 0x2
153#define STATIA2 0x4
154#define STATIA3 0x8
155#define STATIA4 0x10
156#define STATIA5 0x20
157#define STATDA0 0x40
158#define STATDA1 0x80
159
160#endif