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Stefan Roese566806c2007-10-05 17:11:30 +02001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020025#include <asm/ppc4xx.h>
26#include <asm/ppc405.h>
Stefan Roese566806c2007-10-05 17:11:30 +020027#include <libfdt.h>
Stefan Roese8697e6a2007-12-13 14:52:53 +010028#include <fdt_support.h>
Stefan Roese566806c2007-10-05 17:11:30 +020029#include <asm/processor.h>
Stefan Roese353f2682007-10-23 10:10:08 +020030#include <asm/io.h>
Stefan Roese06dfaee2009-10-02 14:35:16 +020031#include <asm/errno.h>
Stefan Roese566806c2007-10-05 17:11:30 +020032
33#if defined(CONFIG_PCI)
34#include <pci.h>
35#include <asm/4xx_pcie.h>
36#endif
37
38DECLARE_GLOBAL_DATA_PTR;
39
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
Stefan Roese566806c2007-10-05 17:11:30 +020041
Stefan Roese9998b132010-01-21 11:37:31 +010042static int board_cpld_version(void)
43{
44 u32 cpld;
45
46 cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
47 if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
48 /*
49 * Magic not found -> "old" CPLD revision which needs
50 * the "old" EBC configuration
51 */
52 mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
53 EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
54 EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
55 EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
56 EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
57 EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
58 EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
59
60 /*
61 * Return 0 for "old" CPLD version
62 */
63 return 0;
64 }
65
66 /*
67 * Magic found -> "new" CPLD revision which needs no new
68 * EBC configuration
69 */
70 return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
71}
72
Stefan Roese566806c2007-10-05 17:11:30 +020073/*
74 * Board early initialization function
75 */
76int board_early_init_f (void)
77{
78 u32 val;
79
80 /*--------------------------------------------------------------------+
81 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
82 +--------------------------------------------------------------------+
83 +---------------------------------------------------------------------+
84 |Interrupt| Source | Pol. | Sensi.| Crit. |
85 +---------+-----------------------------------+-------+-------+-------+
86 | IRQ 00 | UART0 | High | Level | Non |
87 | IRQ 01 | UART1 | High | Level | Non |
88 | IRQ 02 | IIC0 | High | Level | Non |
89 | IRQ 03 | TBD | High | Level | Non |
90 | IRQ 04 | TBD | High | Level | Non |
91 | IRQ 05 | EBM | High | Level | Non |
92 | IRQ 06 | BGI | High | Level | Non |
93 | IRQ 07 | IIC1 | Rising| Edge | Non |
94 | IRQ 08 | SPI | High | Lvl/ed| Non |
95 | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
96 | IRQ 10 | MAL TX EOB | High | Level | Non |
97 | IRQ 11 | MAL RX EOB | High | Level | Non |
98 | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
99 | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
100 | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
101 | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
102 | IRQ 16 | PCIE0 AL | high | Level | Non |
103 | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
104 | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
105 | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
106 | IRQ 20 | PCIE0 TCR | High | Level | Non |
107 | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
108 | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
109 | IRQ 23 | Security EIP-94 | High | Level | Non |
110 | IRQ 24 | EMAC0 interrupt | High | Level | Non |
111 | IRQ 25 | EMAC1 interrupt | High | Level | Non |
112 | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
113 | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
114 | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
115 | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
116 | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
117 | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
118 |----------------------------------------------------------------------
119 | IRQ 32 | MAL Serr | High | Level | Non |
120 | IRQ 33 | MAL Txde | High | Level | Non |
121 | IRQ 34 | MAL Rxde | High | Level | Non |
122 | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
123 | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
124 | IRQ 37 | EBC | High |Lvl Edg| Non |
125 | IRQ 38 | NDFC | High | Level | Non |
126 | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
127 | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
128 | IRQ 41 | PCIE1 AL | high | Level | Non |
129 | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
130 | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
131 | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
132 | IRQ 45 | PCIE1 TCR | High | Level | Non |
133 | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
134 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
135 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
136 | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
137 | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
138 | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
139 | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
140 | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
141 | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
142 | IRQ 55 | Serial ROM | High | Level | Non |
143 | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
144 | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
145 | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
146 | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
147 | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
148 | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
149 | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
150 |----------------------------------------------------------------------
151 | IRQ 64 | PE0 AL | High | Level | Non |
152 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
153 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
154 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
155 | IRQ 68 | PE0 TCR | High | Level | Non |
156 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
157 | IRQ 70 | PE0 DCR Error | High | Level | Non |
158 | IRQ 71 | Reserved | N/A | N/A | Non |
159 | IRQ 72 | PE1 AL | High | Level | Non |
160 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
161 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
162 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
163 | IRQ 76 | PE1 TCR | High | Level | Non |
164 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
165 | IRQ 78 | PE1 DCR Error | High | Level | Non |
166 | IRQ 79 | Reserved | N/A | N/A | Non |
167 | IRQ 80 | PE2 AL | High | Level | Non |
168 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
169 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
170 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
171 | IRQ 84 | PE2 TCR | High | Level | Non |
172 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
173 | IRQ 86 | PE2 DCR Error | High | Level | Non |
174 | IRQ 87 | Reserved | N/A | N/A | Non |
175 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
176 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
177 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
178 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
179 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
180 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
181 | IRQ 94 | Reserved | N/A | N/A | Non |
182 | IRQ 95 | Reserved | N/A | N/A | Non |
183 |---------------------------------------------------------------------
184 +---------+-----------------------------------+-------+-------+------*/
185 /*--------------------------------------------------------------------+
186 | Initialise UIC registers. Clear all interrupts. Disable all
187 | interrupts.
188 | Set critical interrupt values. Set interrupt polarities. Set
189 | interrupt trigger levels. Make bit 0 High priority. Clear all
190 | interrupts again.
191 +-------------------------------------------------------------------*/
192
Stefan Roese952e7762009-09-24 09:55:50 +0200193 mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
194 mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
195 mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
196 mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
197 mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
198 mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
199 mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
200 mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
Stefan Roese566806c2007-10-05 17:11:30 +0200201
Stefan Roese952e7762009-09-24 09:55:50 +0200202 mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
203 mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
204 mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
205 mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
206 mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
207 mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
208 mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
209 mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
Stefan Roese566806c2007-10-05 17:11:30 +0200210
Stefan Roese952e7762009-09-24 09:55:50 +0200211 mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
212 mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
Stefan Roese566806c2007-10-05 17:11:30 +0200213 /* Except cascade UIC0 and UIC1 */
Stefan Roese952e7762009-09-24 09:55:50 +0200214 mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
215 mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
216 mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
217 mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
218 mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
219 mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
Stefan Roese566806c2007-10-05 17:11:30 +0200220
221 /*
222 * Note: Some cores are still in reset when the chip starts, so
223 * take them out of reset
224 */
225 mtsdr(SDR0_SRST, 0);
226
Stefan Roese566806c2007-10-05 17:11:30 +0200227 /* Configure 405EX for NAND usage */
228 val = SDR0_CUST0_MUX_NDFC_SEL |
229 SDR0_CUST0_NDFC_ENABLE |
230 SDR0_CUST0_NDFC_BW_8_BIT |
231 SDR0_CUST0_NRB_BUSY |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
Stefan Roese566806c2007-10-05 17:11:30 +0200233 mtsdr(SDR0_CUST0, val);
234
Stefan Roese7cfc12a2007-12-08 14:47:34 +0100235 /*
236 * Configure PFC (Pin Function Control) registers
237 * -> Enable USB
238 */
239 val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
240 mtsdr(SDR0_PFC1, val);
241
Stefan Roesea0dd99d2008-01-14 10:05:05 +0100242 /*
Stefan Roese9998b132010-01-21 11:37:31 +0100243 * The CPLD version detection has to be the first access to
244 * the CPLD, so we need to make this access this early and
245 * save the CPLD version for later.
246 */
247 gd->board_type = board_cpld_version();
248
249 /*
Stefan Roesea0dd99d2008-01-14 10:05:05 +0100250 * Configure FPGA register with PCIe reset
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252 out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
Stefan Roesea0dd99d2008-01-14 10:05:05 +0100253 mdelay(50);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254 out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
Stefan Roesea0dd99d2008-01-14 10:05:05 +0100255
Stefan Roese566806c2007-10-05 17:11:30 +0200256 return 0;
257}
258
259int misc_init_r(void)
260{
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200261#ifdef CONFIG_ENV_IS_IN_FLASH
Stefan Roese566806c2007-10-05 17:11:30 +0200262 /* Monitor protection ON by default */
263 flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264 -CONFIG_SYS_MONITOR_LEN,
Stefan Roese566806c2007-10-05 17:11:30 +0200265 0xffffffff,
266 &flash_info[0]);
267#endif
268
269 return 0;
270}
271
Stefan Roese70fab192008-05-13 20:22:01 +0200272static int is_405exr(void)
Stefan Roese353f2682007-10-23 10:10:08 +0200273{
274 u32 pvr = get_pvr();
275
Stefan Roese70fab192008-05-13 20:22:01 +0200276 if (pvr & 0x00000004)
277 return 0; /* bit 2 set -> 405EX */
278
279 return 1; /* bit 2 cleared -> 405EXr */
280}
281
282int board_emac_count(void)
283{
Stefan Roese353f2682007-10-23 10:10:08 +0200284 /*
285 * 405EXr only has one EMAC interface, 405EX has two
286 */
Stefan Roese70fab192008-05-13 20:22:01 +0200287 if (is_405exr())
Stefan Roese353f2682007-10-23 10:10:08 +0200288 return 1;
289 else
290 return 2;
291}
292
Stefan Roeseb0b86742009-10-29 15:04:35 +0100293/*
294 * Override the weak default implementation and return the
295 * last PCIe slot number (max number - 1).
296 */
297int board_pcie_last(void)
Stefan Roese353f2682007-10-23 10:10:08 +0200298{
Stefan Roese353f2682007-10-23 10:10:08 +0200299 /*
300 * 405EXr only has one EMAC interface, 405EX has two
301 */
Stefan Roese70fab192008-05-13 20:22:01 +0200302 if (is_405exr())
Stefan Roeseb0b86742009-10-29 15:04:35 +0100303 return 1 - 1;
Stefan Roese353f2682007-10-23 10:10:08 +0200304 else
Stefan Roeseb0b86742009-10-29 15:04:35 +0100305 return 2 - 1;
Stefan Roese353f2682007-10-23 10:10:08 +0200306}
307
Stefan Roese566806c2007-10-05 17:11:30 +0200308int checkboard (void)
309{
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000310 char buf[64];
311 int i = getenv_f("serial#", buf, sizeof(buf));
Stefan Roese566806c2007-10-05 17:11:30 +0200312
Stefan Roese70fab192008-05-13 20:22:01 +0200313 if (is_405exr())
Stefan Roese353f2682007-10-23 10:10:08 +0200314 printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
315 else
316 printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
Stefan Roese566806c2007-10-05 17:11:30 +0200317
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000318 if (i > 0) {
Stefan Roese566806c2007-10-05 17:11:30 +0200319 puts(", serial# ");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000320 puts(buf);
Stefan Roese566806c2007-10-05 17:11:30 +0200321 }
Stefan Roese9998b132010-01-21 11:37:31 +0100322 printf(" (CPLD rev. %ld)\n", gd->board_type);
Stefan Roese566806c2007-10-05 17:11:30 +0200323
324 return (0);
325}