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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stefan Roese19fc2ea2014-10-22 12:13:14 +02002/*
3 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 *
5 * U-Boot version:
Stefan Roesee3b9c982015-11-19 07:46:15 +01006 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
Stefan Roese19fc2ea2014-10-22 12:13:14 +02007 *
8 * Based on the Linux version which is:
9 * Copyright (C) 2012 Marvell
10 *
11 * Rami Rosen <rosenr@marvell.com>
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020013 */
14
15#include <common.h>
Stefan Roesee3b9c982015-11-19 07:46:15 +010016#include <dm.h>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020017#include <net.h>
18#include <netdev.h>
19#include <config.h>
20#include <malloc.h>
21#include <asm/io.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090022#include <linux/errno.h>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020023#include <phy.h>
24#include <miiphy.h>
25#include <watchdog.h>
26#include <asm/arch/cpu.h>
27#include <asm/arch/soc.h>
28#include <linux/compat.h>
29#include <linux/mbus.h>
30
Stefan Roesee3b9c982015-11-19 07:46:15 +010031DECLARE_GLOBAL_DATA_PTR;
32
Stefan Roese19fc2ea2014-10-22 12:13:14 +020033#if !defined(CONFIG_PHYLIB)
34# error Marvell mvneta requires PHYLIB
35#endif
36
37/* Some linux -> U-Boot compatibility stuff */
38#define netdev_err(dev, fmt, args...) \
39 printf(fmt, ##args)
40#define netdev_warn(dev, fmt, args...) \
41 printf(fmt, ##args)
42#define netdev_info(dev, fmt, args...) \
43 printf(fmt, ##args)
44
45#define CONFIG_NR_CPUS 1
Stefan Roese19fc2ea2014-10-22 12:13:14 +020046#define ETH_HLEN 14 /* Total octets in header */
47
48/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
49#define WRAP (2 + ETH_HLEN + 4 + 32)
50#define MTU 1500
51#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
52
53#define MVNETA_SMI_TIMEOUT 10000
54
55/* Registers */
56#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
57#define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
58#define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
59#define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
60#define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
61#define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
62#define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
63#define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
64#define MVNETA_RXQ_BUF_SIZE_SHIFT 19
65#define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
66#define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
67#define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
68#define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
69#define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
70#define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
71#define MVNETA_PORT_RX_RESET 0x1cc0
72#define MVNETA_PORT_RX_DMA_RESET BIT(0)
73#define MVNETA_PHY_ADDR 0x2000
74#define MVNETA_PHY_ADDR_MASK 0x1f
75#define MVNETA_SMI 0x2004
76#define MVNETA_PHY_REG_MASK 0x1f
77/* SMI register fields */
78#define MVNETA_SMI_DATA_OFFS 0 /* Data */
79#define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
80#define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
81#define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
82#define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
83#define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
84#define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
85#define MVNETA_SMI_BUSY (1 << 28) /* Busy */
86#define MVNETA_MBUS_RETRY 0x2010
87#define MVNETA_UNIT_INTR_CAUSE 0x2080
88#define MVNETA_UNIT_CONTROL 0x20B0
89#define MVNETA_PHY_POLLING_ENABLE BIT(1)
90#define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
91#define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
92#define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
Stefan Roese544eefe2016-05-19 17:46:36 +020093#define MVNETA_WIN_SIZE_MASK (0xffff0000)
Stefan Roese19fc2ea2014-10-22 12:13:14 +020094#define MVNETA_BASE_ADDR_ENABLE 0x2290
Stefan Roese544eefe2016-05-19 17:46:36 +020095#define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
96#define MVNETA_PORT_ACCESS_PROTECT 0x2294
97#define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
Stefan Roese19fc2ea2014-10-22 12:13:14 +020098#define MVNETA_PORT_CONFIG 0x2400
99#define MVNETA_UNI_PROMISC_MODE BIT(0)
100#define MVNETA_DEF_RXQ(q) ((q) << 1)
101#define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
102#define MVNETA_TX_UNSET_ERR_SUM BIT(12)
103#define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
104#define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
105#define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
106#define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
107#define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
108 MVNETA_DEF_RXQ_ARP(q) | \
109 MVNETA_DEF_RXQ_TCP(q) | \
110 MVNETA_DEF_RXQ_UDP(q) | \
111 MVNETA_DEF_RXQ_BPDU(q) | \
112 MVNETA_TX_UNSET_ERR_SUM | \
113 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
114#define MVNETA_PORT_CONFIG_EXTEND 0x2404
115#define MVNETA_MAC_ADDR_LOW 0x2414
116#define MVNETA_MAC_ADDR_HIGH 0x2418
117#define MVNETA_SDMA_CONFIG 0x241c
118#define MVNETA_SDMA_BRST_SIZE_16 4
119#define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
120#define MVNETA_RX_NO_DATA_SWAP BIT(4)
121#define MVNETA_TX_NO_DATA_SWAP BIT(5)
122#define MVNETA_DESC_SWAP BIT(6)
123#define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
124#define MVNETA_PORT_STATUS 0x2444
125#define MVNETA_TX_IN_PRGRS BIT(1)
126#define MVNETA_TX_FIFO_EMPTY BIT(8)
127#define MVNETA_RX_MIN_FRAME_SIZE 0x247c
128#define MVNETA_SERDES_CFG 0x24A0
129#define MVNETA_SGMII_SERDES_PROTO 0x0cc7
130#define MVNETA_QSGMII_SERDES_PROTO 0x0667
131#define MVNETA_TYPE_PRIO 0x24bc
132#define MVNETA_FORCE_UNI BIT(21)
133#define MVNETA_TXQ_CMD_1 0x24e4
134#define MVNETA_TXQ_CMD 0x2448
135#define MVNETA_TXQ_DISABLE_SHIFT 8
136#define MVNETA_TXQ_ENABLE_MASK 0x000000ff
137#define MVNETA_ACC_MODE 0x2500
138#define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
139#define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
140#define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
141#define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
142
143/* Exception Interrupt Port/Queue Cause register */
144
145#define MVNETA_INTR_NEW_CAUSE 0x25a0
146#define MVNETA_INTR_NEW_MASK 0x25a4
147
148/* bits 0..7 = TXQ SENT, one bit per queue.
149 * bits 8..15 = RXQ OCCUP, one bit per queue.
150 * bits 16..23 = RXQ FREE, one bit per queue.
151 * bit 29 = OLD_REG_SUM, see old reg ?
152 * bit 30 = TX_ERR_SUM, one bit for 4 ports
153 * bit 31 = MISC_SUM, one bit for 4 ports
154 */
155#define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
156#define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
157#define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
158#define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
159
160#define MVNETA_INTR_OLD_CAUSE 0x25a8
161#define MVNETA_INTR_OLD_MASK 0x25ac
162
163/* Data Path Port/Queue Cause Register */
164#define MVNETA_INTR_MISC_CAUSE 0x25b0
165#define MVNETA_INTR_MISC_MASK 0x25b4
166#define MVNETA_INTR_ENABLE 0x25b8
167
168#define MVNETA_RXQ_CMD 0x2680
169#define MVNETA_RXQ_DISABLE_SHIFT 8
170#define MVNETA_RXQ_ENABLE_MASK 0x000000ff
171#define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
172#define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
173#define MVNETA_GMAC_CTRL_0 0x2c00
174#define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
175#define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
176#define MVNETA_GMAC0_PORT_ENABLE BIT(0)
177#define MVNETA_GMAC_CTRL_2 0x2c08
178#define MVNETA_GMAC2_PCS_ENABLE BIT(3)
179#define MVNETA_GMAC2_PORT_RGMII BIT(4)
180#define MVNETA_GMAC2_PORT_RESET BIT(6)
181#define MVNETA_GMAC_STATUS 0x2c10
182#define MVNETA_GMAC_LINK_UP BIT(0)
183#define MVNETA_GMAC_SPEED_1000 BIT(1)
184#define MVNETA_GMAC_SPEED_100 BIT(2)
185#define MVNETA_GMAC_FULL_DUPLEX BIT(3)
186#define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
187#define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
188#define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
189#define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
190#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
191#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
192#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200193#define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
194#define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200195#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
196#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
197#define MVNETA_GMAC_AN_SPEED_EN BIT(7)
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200198#define MVNETA_GMAC_SET_FC_EN BIT(8)
199#define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200200#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
201#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200202#define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200203#define MVNETA_MIB_COUNTERS_BASE 0x3080
204#define MVNETA_MIB_LATE_COLLISION 0x7c
205#define MVNETA_DA_FILT_SPEC_MCAST 0x3400
206#define MVNETA_DA_FILT_OTH_MCAST 0x3500
207#define MVNETA_DA_FILT_UCAST_BASE 0x3600
208#define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
209#define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
210#define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
211#define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
212#define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
213#define MVNETA_TXQ_DEC_SENT_SHIFT 16
214#define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
215#define MVNETA_TXQ_SENT_DESC_SHIFT 16
216#define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
217#define MVNETA_PORT_TX_RESET 0x3cf0
218#define MVNETA_PORT_TX_DMA_RESET BIT(0)
219#define MVNETA_TX_MTU 0x3e0c
220#define MVNETA_TX_TOKEN_SIZE 0x3e14
221#define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
222#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
223#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
224
225/* Descriptor ring Macros */
226#define MVNETA_QUEUE_NEXT_DESC(q, index) \
227 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
228
229/* Various constants */
230
231/* Coalescing */
232#define MVNETA_TXDONE_COAL_PKTS 16
233#define MVNETA_RX_COAL_PKTS 32
234#define MVNETA_RX_COAL_USEC 100
235
236/* The two bytes Marvell header. Either contains a special value used
237 * by Marvell switches when a specific hardware mode is enabled (not
238 * supported by this driver) or is filled automatically by zeroes on
239 * the RX side. Those two bytes being at the front of the Ethernet
240 * header, they allow to have the IP header aligned on a 4 bytes
241 * boundary automatically: the hardware skips those two bytes on its
242 * own.
243 */
244#define MVNETA_MH_SIZE 2
245
246#define MVNETA_VLAN_TAG_LEN 4
247
248#define MVNETA_CPU_D_CACHE_LINE_SIZE 32
249#define MVNETA_TX_CSUM_MAX_SIZE 9800
250#define MVNETA_ACC_MODE_EXT 1
251
252/* Timeout constants */
253#define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
254#define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
255#define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
256
257#define MVNETA_TX_MTU_MAX 0x3ffff
258
259/* Max number of Rx descriptors */
260#define MVNETA_MAX_RXD 16
261
262/* Max number of Tx descriptors */
263#define MVNETA_MAX_TXD 16
264
265/* descriptor aligned size */
266#define MVNETA_DESC_ALIGNED_SIZE 32
267
268struct mvneta_port {
269 void __iomem *base;
270 struct mvneta_rx_queue *rxqs;
271 struct mvneta_tx_queue *txqs;
272
273 u8 mcast_count[256];
274 u16 tx_ring_size;
275 u16 rx_ring_size;
276
277 phy_interface_t phy_interface;
278 unsigned int link;
279 unsigned int duplex;
280 unsigned int speed;
281
282 int init;
283 int phyaddr;
284 struct phy_device *phydev;
285 struct mii_dev *bus;
286};
287
288/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
289 * layout of the transmit and reception DMA descriptors, and their
290 * layout is therefore defined by the hardware design
291 */
292
293#define MVNETA_TX_L3_OFF_SHIFT 0
294#define MVNETA_TX_IP_HLEN_SHIFT 8
295#define MVNETA_TX_L4_UDP BIT(16)
296#define MVNETA_TX_L3_IP6 BIT(17)
297#define MVNETA_TXD_IP_CSUM BIT(18)
298#define MVNETA_TXD_Z_PAD BIT(19)
299#define MVNETA_TXD_L_DESC BIT(20)
300#define MVNETA_TXD_F_DESC BIT(21)
301#define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
302 MVNETA_TXD_L_DESC | \
303 MVNETA_TXD_F_DESC)
304#define MVNETA_TX_L4_CSUM_FULL BIT(30)
305#define MVNETA_TX_L4_CSUM_NOT BIT(31)
306
307#define MVNETA_RXD_ERR_CRC 0x0
308#define MVNETA_RXD_ERR_SUMMARY BIT(16)
309#define MVNETA_RXD_ERR_OVERRUN BIT(17)
310#define MVNETA_RXD_ERR_LEN BIT(18)
311#define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
312#define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
313#define MVNETA_RXD_L3_IP4 BIT(25)
314#define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
315#define MVNETA_RXD_L4_CSUM_OK BIT(30)
316
317struct mvneta_tx_desc {
318 u32 command; /* Options used by HW for packet transmitting.*/
319 u16 reserverd1; /* csum_l4 (for future use) */
320 u16 data_size; /* Data size of transmitted packet in bytes */
321 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
322 u32 reserved2; /* hw_cmd - (for future use, PMT) */
323 u32 reserved3[4]; /* Reserved - (for future use) */
324};
325
326struct mvneta_rx_desc {
327 u32 status; /* Info about received packet */
328 u16 reserved1; /* pnc_info - (for future use, PnC) */
329 u16 data_size; /* Size of received packet in bytes */
330
331 u32 buf_phys_addr; /* Physical address of the buffer */
332 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
333
334 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
335 u16 reserved3; /* prefetch_cmd, for future use */
336 u16 reserved4; /* csum_l4 - (for future use, PnC) */
337
338 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
339 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
340};
341
342struct mvneta_tx_queue {
343 /* Number of this TX queue, in the range 0-7 */
344 u8 id;
345
346 /* Number of TX DMA descriptors in the descriptor ring */
347 int size;
348
349 /* Index of last TX DMA descriptor that was inserted */
350 int txq_put_index;
351
352 /* Index of the TX DMA descriptor to be cleaned up */
353 int txq_get_index;
354
355 /* Virtual address of the TX DMA descriptors array */
356 struct mvneta_tx_desc *descs;
357
358 /* DMA address of the TX DMA descriptors array */
359 dma_addr_t descs_phys;
360
361 /* Index of the last TX DMA descriptor */
362 int last_desc;
363
364 /* Index of the next TX DMA descriptor to process */
365 int next_desc_to_proc;
366};
367
368struct mvneta_rx_queue {
369 /* rx queue number, in the range 0-7 */
370 u8 id;
371
372 /* num of rx descriptors in the rx descriptor ring */
373 int size;
374
375 /* Virtual address of the RX DMA descriptors array */
376 struct mvneta_rx_desc *descs;
377
378 /* DMA address of the RX DMA descriptors array */
379 dma_addr_t descs_phys;
380
381 /* Index of the last RX DMA descriptor */
382 int last_desc;
383
384 /* Index of the next RX DMA descriptor to process */
385 int next_desc_to_proc;
386};
387
388/* U-Boot doesn't use the queues, so set the number to 1 */
389static int rxq_number = 1;
390static int txq_number = 1;
391static int rxq_def;
392
393struct buffer_location {
394 struct mvneta_tx_desc *tx_descs;
395 struct mvneta_rx_desc *rx_descs;
396 u32 rx_buffers;
397};
398
399/*
400 * All 4 interfaces use the same global buffer, since only one interface
401 * can be enabled at once
402 */
403static struct buffer_location buffer_loc;
404
405/*
406 * Page table entries are set to 1MB, or multiples of 1MB
407 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
408 */
409#define BD_SPACE (1 << 20)
410
Konstantin Porotchkin976feda2017-02-16 13:52:27 +0200411/*
412 * Dummy implementation that can be overwritten by a board
413 * specific function
414 */
415__weak int board_network_enable(struct mii_dev *bus)
416{
417 return 0;
418}
419
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200420/* Utility/helper methods */
421
422/* Write helper method */
423static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
424{
425 writel(data, pp->base + offset);
426}
427
428/* Read helper method */
429static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
430{
431 return readl(pp->base + offset);
432}
433
434/* Clear all MIB counters */
435static void mvneta_mib_counters_clear(struct mvneta_port *pp)
436{
437 int i;
438
439 /* Perform dummy reads from MIB counters */
440 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
441 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
442}
443
444/* Rx descriptors helper methods */
445
446/* Checks whether the RX descriptor having this status is both the first
447 * and the last descriptor for the RX packet. Each RX packet is currently
448 * received through a single RX descriptor, so not having each RX
449 * descriptor with its first and last bits set is an error
450 */
451static int mvneta_rxq_desc_is_first_last(u32 status)
452{
453 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
454 MVNETA_RXD_FIRST_LAST_DESC;
455}
456
457/* Add number of descriptors ready to receive new packets */
458static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
459 struct mvneta_rx_queue *rxq,
460 int ndescs)
461{
462 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
463 * be added at once
464 */
465 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
466 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
467 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
468 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
469 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
470 }
471
472 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
473 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
474}
475
476/* Get number of RX descriptors occupied by received packets */
477static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
478 struct mvneta_rx_queue *rxq)
479{
480 u32 val;
481
482 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
483 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
484}
485
486/* Update num of rx desc called upon return from rx path or
487 * from mvneta_rxq_drop_pkts().
488 */
489static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
490 struct mvneta_rx_queue *rxq,
491 int rx_done, int rx_filled)
492{
493 u32 val;
494
495 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
496 val = rx_done |
497 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
498 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
499 return;
500 }
501
502 /* Only 255 descriptors can be added at once */
503 while ((rx_done > 0) || (rx_filled > 0)) {
504 if (rx_done <= 0xff) {
505 val = rx_done;
506 rx_done = 0;
507 } else {
508 val = 0xff;
509 rx_done -= 0xff;
510 }
511 if (rx_filled <= 0xff) {
512 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
513 rx_filled = 0;
514 } else {
515 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
516 rx_filled -= 0xff;
517 }
518 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
519 }
520}
521
522/* Get pointer to next RX descriptor to be processed by SW */
523static struct mvneta_rx_desc *
524mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
525{
526 int rx_desc = rxq->next_desc_to_proc;
527
528 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
529 return rxq->descs + rx_desc;
530}
531
532/* Tx descriptors helper methods */
533
534/* Update HW with number of TX descriptors to be sent */
535static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
536 struct mvneta_tx_queue *txq,
537 int pend_desc)
538{
539 u32 val;
540
541 /* Only 255 descriptors can be added at once ; Assume caller
Heinrich Schuchardte4691562017-08-29 18:44:37 +0200542 * process TX descriptors in quanta less than 256
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200543 */
544 val = pend_desc;
545 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
546}
547
548/* Get pointer to next TX descriptor to be processed (send) by HW */
549static struct mvneta_tx_desc *
550mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
551{
552 int tx_desc = txq->next_desc_to_proc;
553
554 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
555 return txq->descs + tx_desc;
556}
557
558/* Set rxq buf size */
559static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
560 struct mvneta_rx_queue *rxq,
561 int buf_size)
562{
563 u32 val;
564
565 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
566
567 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
568 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
569
570 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
571}
572
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200573static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
574{
575 /* phy_addr is set to invalid value for fixed link */
576 return pp->phyaddr > PHY_MAX_ADDR;
577}
578
579
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200580/* Start the Ethernet port RX and TX activity */
581static void mvneta_port_up(struct mvneta_port *pp)
582{
583 int queue;
584 u32 q_map;
585
586 /* Enable all initialized TXs. */
587 mvneta_mib_counters_clear(pp);
588 q_map = 0;
589 for (queue = 0; queue < txq_number; queue++) {
590 struct mvneta_tx_queue *txq = &pp->txqs[queue];
591 if (txq->descs != NULL)
592 q_map |= (1 << queue);
593 }
594 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
595
596 /* Enable all initialized RXQs. */
597 q_map = 0;
598 for (queue = 0; queue < rxq_number; queue++) {
599 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
600 if (rxq->descs != NULL)
601 q_map |= (1 << queue);
602 }
603 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
604}
605
606/* Stop the Ethernet port activity */
607static void mvneta_port_down(struct mvneta_port *pp)
608{
609 u32 val;
610 int count;
611
612 /* Stop Rx port activity. Check port Rx activity. */
613 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
614
615 /* Issue stop command for active channels only */
616 if (val != 0)
617 mvreg_write(pp, MVNETA_RXQ_CMD,
618 val << MVNETA_RXQ_DISABLE_SHIFT);
619
620 /* Wait for all Rx activity to terminate. */
621 count = 0;
622 do {
623 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
624 netdev_warn(pp->dev,
625 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
626 val);
627 break;
628 }
629 mdelay(1);
630
631 val = mvreg_read(pp, MVNETA_RXQ_CMD);
632 } while (val & 0xff);
633
634 /* Stop Tx port activity. Check port Tx activity. Issue stop
635 * command for active channels only
636 */
637 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
638
639 if (val != 0)
640 mvreg_write(pp, MVNETA_TXQ_CMD,
641 (val << MVNETA_TXQ_DISABLE_SHIFT));
642
643 /* Wait for all Tx activity to terminate. */
644 count = 0;
645 do {
646 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
647 netdev_warn(pp->dev,
648 "TIMEOUT for TX stopped status=0x%08x\n",
649 val);
650 break;
651 }
652 mdelay(1);
653
654 /* Check TX Command reg that all Txqs are stopped */
655 val = mvreg_read(pp, MVNETA_TXQ_CMD);
656
657 } while (val & 0xff);
658
659 /* Double check to verify that TX FIFO is empty */
660 count = 0;
661 do {
662 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
663 netdev_warn(pp->dev,
664 "TX FIFO empty timeout status=0x08%x\n",
665 val);
666 break;
667 }
668 mdelay(1);
669
670 val = mvreg_read(pp, MVNETA_PORT_STATUS);
671 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
672 (val & MVNETA_TX_IN_PRGRS));
673
674 udelay(200);
675}
676
677/* Enable the port by setting the port enable bit of the MAC control register */
678static void mvneta_port_enable(struct mvneta_port *pp)
679{
680 u32 val;
681
682 /* Enable port */
683 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
684 val |= MVNETA_GMAC0_PORT_ENABLE;
685 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
686}
687
688/* Disable the port and wait for about 200 usec before retuning */
689static void mvneta_port_disable(struct mvneta_port *pp)
690{
691 u32 val;
692
693 /* Reset the Enable bit in the Serial Control Register */
694 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
695 val &= ~MVNETA_GMAC0_PORT_ENABLE;
696 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
697
698 udelay(200);
699}
700
701/* Multicast tables methods */
702
703/* Set all entries in Unicast MAC Table; queue==-1 means reject all */
704static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
705{
706 int offset;
707 u32 val;
708
709 if (queue == -1) {
710 val = 0;
711 } else {
712 val = 0x1 | (queue << 1);
713 val |= (val << 24) | (val << 16) | (val << 8);
714 }
715
716 for (offset = 0; offset <= 0xc; offset += 4)
717 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
718}
719
720/* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
721static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
722{
723 int offset;
724 u32 val;
725
726 if (queue == -1) {
727 val = 0;
728 } else {
729 val = 0x1 | (queue << 1);
730 val |= (val << 24) | (val << 16) | (val << 8);
731 }
732
733 for (offset = 0; offset <= 0xfc; offset += 4)
734 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
735}
736
737/* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
738static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
739{
740 int offset;
741 u32 val;
742
743 if (queue == -1) {
744 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
745 val = 0;
746 } else {
747 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
748 val = 0x1 | (queue << 1);
749 val |= (val << 24) | (val << 16) | (val << 8);
750 }
751
752 for (offset = 0; offset <= 0xfc; offset += 4)
753 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
754}
755
756/* This method sets defaults to the NETA port:
757 * Clears interrupt Cause and Mask registers.
758 * Clears all MAC tables.
759 * Sets defaults to all registers.
760 * Resets RX and TX descriptor rings.
761 * Resets PHY.
762 * This method can be called after mvneta_port_down() to return the port
763 * settings to defaults.
764 */
765static void mvneta_defaults_set(struct mvneta_port *pp)
766{
767 int cpu;
768 int queue;
769 u32 val;
770
771 /* Clear all Cause registers */
772 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
773 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
774 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
775
776 /* Mask all interrupts */
777 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
778 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
779 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
780 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
781
782 /* Enable MBUS Retry bit16 */
783 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
784
785 /* Set CPU queue access map - all CPUs have access to all RX
786 * queues and to all TX queues
787 */
788 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
789 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
790 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
791 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
792
793 /* Reset RX and TX DMAs */
794 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
795 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
796
797 /* Disable Legacy WRR, Disable EJP, Release from reset */
798 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
799 for (queue = 0; queue < txq_number; queue++) {
800 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
801 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
802 }
803
804 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
805 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
806
807 /* Set Port Acceleration Mode */
808 val = MVNETA_ACC_MODE_EXT;
809 mvreg_write(pp, MVNETA_ACC_MODE, val);
810
811 /* Update val of portCfg register accordingly with all RxQueue types */
812 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
813 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
814
815 val = 0;
816 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
817 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
818
819 /* Build PORT_SDMA_CONFIG_REG */
820 val = 0;
821
822 /* Default burst size */
823 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
824 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
825 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
826
827 /* Assign port SDMA configuration */
828 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
829
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200830 /* Enable PHY polling in hardware if not in fixed-link mode */
831 if (!mvneta_port_is_fixed_link(pp)) {
832 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
833 val |= MVNETA_PHY_POLLING_ENABLE;
834 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
835 }
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200836
837 mvneta_set_ucast_table(pp, -1);
838 mvneta_set_special_mcast_table(pp, -1);
839 mvneta_set_other_mcast_table(pp, -1);
840}
841
842/* Set unicast address */
843static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
844 int queue)
845{
846 unsigned int unicast_reg;
847 unsigned int tbl_offset;
848 unsigned int reg_offset;
849
850 /* Locate the Unicast table entry */
851 last_nibble = (0xf & last_nibble);
852
853 /* offset from unicast tbl base */
854 tbl_offset = (last_nibble / 4) * 4;
855
856 /* offset within the above reg */
857 reg_offset = last_nibble % 4;
858
859 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
860
861 if (queue == -1) {
862 /* Clear accepts frame bit at specified unicast DA tbl entry */
863 unicast_reg &= ~(0xff << (8 * reg_offset));
864 } else {
865 unicast_reg &= ~(0xff << (8 * reg_offset));
866 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
867 }
868
869 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
870}
871
872/* Set mac address */
873static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
874 int queue)
875{
876 unsigned int mac_h;
877 unsigned int mac_l;
878
879 if (queue != -1) {
880 mac_l = (addr[4] << 8) | (addr[5]);
881 mac_h = (addr[0] << 24) | (addr[1] << 16) |
882 (addr[2] << 8) | (addr[3] << 0);
883
884 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
885 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
886 }
887
888 /* Accept frames of this address */
889 mvneta_set_ucast_addr(pp, addr[5], queue);
890}
891
Matt Pelland0a85f022018-03-27 13:18:25 -0400892static int mvneta_write_hwaddr(struct udevice *dev)
893{
894 mvneta_mac_addr_set(dev_get_priv(dev),
895 ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr,
896 rxq_def);
897
898 return 0;
899}
900
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200901/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
902static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
903 u32 phys_addr, u32 cookie)
904{
905 rx_desc->buf_cookie = cookie;
906 rx_desc->buf_phys_addr = phys_addr;
907}
908
909/* Decrement sent descriptors counter */
910static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
911 struct mvneta_tx_queue *txq,
912 int sent_desc)
913{
914 u32 val;
915
916 /* Only 255 TX descriptors can be updated at once */
917 while (sent_desc > 0xff) {
918 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
919 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
920 sent_desc = sent_desc - 0xff;
921 }
922
923 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
924 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
925}
926
927/* Get number of TX descriptors already sent by HW */
928static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
929 struct mvneta_tx_queue *txq)
930{
931 u32 val;
932 int sent_desc;
933
934 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
935 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
936 MVNETA_TXQ_SENT_DESC_SHIFT;
937
938 return sent_desc;
939}
940
941/* Display more error info */
942static void mvneta_rx_error(struct mvneta_port *pp,
943 struct mvneta_rx_desc *rx_desc)
944{
945 u32 status = rx_desc->status;
946
947 if (!mvneta_rxq_desc_is_first_last(status)) {
948 netdev_err(pp->dev,
949 "bad rx status %08x (buffer oversize), size=%d\n",
950 status, rx_desc->data_size);
951 return;
952 }
953
954 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
955 case MVNETA_RXD_ERR_CRC:
956 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
957 status, rx_desc->data_size);
958 break;
959 case MVNETA_RXD_ERR_OVERRUN:
960 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
961 status, rx_desc->data_size);
962 break;
963 case MVNETA_RXD_ERR_LEN:
964 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
965 status, rx_desc->data_size);
966 break;
967 case MVNETA_RXD_ERR_RESOURCE:
968 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
969 status, rx_desc->data_size);
970 break;
971 }
972}
973
974static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
975 int rxq)
976{
977 return &pp->rxqs[rxq];
978}
979
980
981/* Drop packets received by the RXQ and free buffers */
982static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
983 struct mvneta_rx_queue *rxq)
984{
985 int rx_done;
986
987 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
988 if (rx_done)
989 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
990}
991
992/* Handle rxq fill: allocates rxq skbs; called when initializing a port */
993static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
994 int num)
995{
996 int i;
997
998 for (i = 0; i < num; i++) {
999 u32 addr;
1000
1001 /* U-Boot special: Fill in the rx buffer addresses */
1002 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
1003 mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
1004 }
1005
1006 /* Add this number of RX descriptors as non occupied (ready to
1007 * get packets)
1008 */
1009 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1010
1011 return 0;
1012}
1013
1014/* Rx/Tx queue initialization/cleanup methods */
1015
1016/* Create a specified RX queue */
1017static int mvneta_rxq_init(struct mvneta_port *pp,
1018 struct mvneta_rx_queue *rxq)
1019
1020{
1021 rxq->size = pp->rx_ring_size;
1022
1023 /* Allocate memory for RX descriptors */
1024 rxq->descs_phys = (dma_addr_t)rxq->descs;
1025 if (rxq->descs == NULL)
1026 return -ENOMEM;
1027
Jon Nettleton199b27b2018-05-30 08:52:29 +03001028 WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN));
1029
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001030 rxq->last_desc = rxq->size - 1;
1031
1032 /* Set Rx descriptors queue starting address */
1033 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
1034 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
1035
1036 /* Fill RXQ with buffers from RX pool */
1037 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
1038 mvneta_rxq_fill(pp, rxq, rxq->size);
1039
1040 return 0;
1041}
1042
1043/* Cleanup Rx queue */
1044static void mvneta_rxq_deinit(struct mvneta_port *pp,
1045 struct mvneta_rx_queue *rxq)
1046{
1047 mvneta_rxq_drop_pkts(pp, rxq);
1048
1049 rxq->descs = NULL;
1050 rxq->last_desc = 0;
1051 rxq->next_desc_to_proc = 0;
1052 rxq->descs_phys = 0;
1053}
1054
1055/* Create and initialize a tx queue */
1056static int mvneta_txq_init(struct mvneta_port *pp,
1057 struct mvneta_tx_queue *txq)
1058{
1059 txq->size = pp->tx_ring_size;
1060
1061 /* Allocate memory for TX descriptors */
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001062 txq->descs_phys = (dma_addr_t)txq->descs;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001063 if (txq->descs == NULL)
1064 return -ENOMEM;
1065
Jon Nettleton199b27b2018-05-30 08:52:29 +03001066 WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN));
1067
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001068 txq->last_desc = txq->size - 1;
1069
1070 /* Set maximum bandwidth for enabled TXQs */
1071 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
1072 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
1073
1074 /* Set Tx descriptors queue starting address */
1075 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
1076 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
1077
1078 return 0;
1079}
1080
1081/* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
1082static void mvneta_txq_deinit(struct mvneta_port *pp,
1083 struct mvneta_tx_queue *txq)
1084{
1085 txq->descs = NULL;
1086 txq->last_desc = 0;
1087 txq->next_desc_to_proc = 0;
1088 txq->descs_phys = 0;
1089
1090 /* Set minimum bandwidth for disabled TXQs */
1091 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
1092 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
1093
1094 /* Set Tx descriptors queue starting address and size */
1095 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
1096 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
1097}
1098
1099/* Cleanup all Tx queues */
1100static void mvneta_cleanup_txqs(struct mvneta_port *pp)
1101{
1102 int queue;
1103
1104 for (queue = 0; queue < txq_number; queue++)
1105 mvneta_txq_deinit(pp, &pp->txqs[queue]);
1106}
1107
1108/* Cleanup all Rx queues */
1109static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
1110{
1111 int queue;
1112
1113 for (queue = 0; queue < rxq_number; queue++)
1114 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
1115}
1116
1117
1118/* Init all Rx queues */
1119static int mvneta_setup_rxqs(struct mvneta_port *pp)
1120{
1121 int queue;
1122
1123 for (queue = 0; queue < rxq_number; queue++) {
1124 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
1125 if (err) {
1126 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
1127 __func__, queue);
1128 mvneta_cleanup_rxqs(pp);
1129 return err;
1130 }
1131 }
1132
1133 return 0;
1134}
1135
1136/* Init all tx queues */
1137static int mvneta_setup_txqs(struct mvneta_port *pp)
1138{
1139 int queue;
1140
1141 for (queue = 0; queue < txq_number; queue++) {
1142 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
1143 if (err) {
1144 netdev_err(pp->dev, "%s: can't create txq=%d\n",
1145 __func__, queue);
1146 mvneta_cleanup_txqs(pp);
1147 return err;
1148 }
1149 }
1150
1151 return 0;
1152}
1153
1154static void mvneta_start_dev(struct mvneta_port *pp)
1155{
1156 /* start the Rx/Tx activity */
1157 mvneta_port_enable(pp);
1158}
1159
Stefan Roesee3b9c982015-11-19 07:46:15 +01001160static void mvneta_adjust_link(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001161{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001162 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001163 struct phy_device *phydev = pp->phydev;
1164 int status_change = 0;
1165
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001166 if (mvneta_port_is_fixed_link(pp)) {
1167 debug("Using fixed link, skip link adjust\n");
1168 return;
1169 }
1170
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001171 if (phydev->link) {
1172 if ((pp->speed != phydev->speed) ||
1173 (pp->duplex != phydev->duplex)) {
1174 u32 val;
1175
1176 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1177 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
1178 MVNETA_GMAC_CONFIG_GMII_SPEED |
1179 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
1180 MVNETA_GMAC_AN_SPEED_EN |
1181 MVNETA_GMAC_AN_DUPLEX_EN);
1182
1183 if (phydev->duplex)
1184 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1185
1186 if (phydev->speed == SPEED_1000)
1187 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1188 else
1189 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1190
1191 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1192
1193 pp->duplex = phydev->duplex;
1194 pp->speed = phydev->speed;
1195 }
1196 }
1197
1198 if (phydev->link != pp->link) {
1199 if (!phydev->link) {
1200 pp->duplex = -1;
1201 pp->speed = 0;
1202 }
1203
1204 pp->link = phydev->link;
1205 status_change = 1;
1206 }
1207
1208 if (status_change) {
1209 if (phydev->link) {
1210 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1211 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
1212 MVNETA_GMAC_FORCE_LINK_DOWN);
1213 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1214 mvneta_port_up(pp);
1215 } else {
1216 mvneta_port_down(pp);
1217 }
1218 }
1219}
1220
Stefan Roesee3b9c982015-11-19 07:46:15 +01001221static int mvneta_open(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001222{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001223 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001224 int ret;
1225
1226 ret = mvneta_setup_rxqs(pp);
1227 if (ret)
1228 return ret;
1229
1230 ret = mvneta_setup_txqs(pp);
1231 if (ret)
1232 return ret;
1233
1234 mvneta_adjust_link(dev);
1235
1236 mvneta_start_dev(pp);
1237
1238 return 0;
1239}
1240
1241/* Initialize hw */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001242static int mvneta_init2(struct mvneta_port *pp)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001243{
1244 int queue;
1245
1246 /* Disable port */
1247 mvneta_port_disable(pp);
1248
1249 /* Set port default values */
1250 mvneta_defaults_set(pp);
1251
1252 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
1253 GFP_KERNEL);
1254 if (!pp->txqs)
1255 return -ENOMEM;
1256
1257 /* U-Boot special: use preallocated area */
1258 pp->txqs[0].descs = buffer_loc.tx_descs;
1259
1260 /* Initialize TX descriptor rings */
1261 for (queue = 0; queue < txq_number; queue++) {
1262 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1263 txq->id = queue;
1264 txq->size = pp->tx_ring_size;
1265 }
1266
1267 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
1268 GFP_KERNEL);
1269 if (!pp->rxqs) {
1270 kfree(pp->txqs);
1271 return -ENOMEM;
1272 }
1273
1274 /* U-Boot special: use preallocated area */
1275 pp->rxqs[0].descs = buffer_loc.rx_descs;
1276
1277 /* Create Rx descriptor rings */
1278 for (queue = 0; queue < rxq_number; queue++) {
1279 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1280 rxq->id = queue;
1281 rxq->size = pp->rx_ring_size;
1282 }
1283
1284 return 0;
1285}
1286
1287/* platform glue : initialize decoding windows */
Stefan Roese544eefe2016-05-19 17:46:36 +02001288
1289/*
1290 * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
1291 * First layer is: GbE Address window that resides inside the GBE unit,
1292 * Second layer is: Fabric address window which is located in the NIC400
1293 * (South Fabric).
1294 * To simplify the address decode configuration for Armada3700, we bypass the
1295 * first layer of GBE decode window by setting the first window to 4GB.
1296 */
1297static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
1298{
1299 /*
1300 * Set window size to 4GB, to bypass GBE address decode, leave the
1301 * work to MBUS decode window
1302 */
1303 mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
1304
1305 /* Enable GBE address decode window 0 by set bit 0 to 0 */
1306 clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
1307 MVNETA_BASE_ADDR_ENABLE_BIT);
1308
1309 /* Set GBE address decode window 0 to full Access (read or write) */
1310 setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
1311 MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
1312}
1313
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001314static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
1315{
1316 const struct mbus_dram_target_info *dram;
1317 u32 win_enable;
1318 u32 win_protect;
1319 int i;
1320
1321 dram = mvebu_mbus_dram_info();
1322 for (i = 0; i < 6; i++) {
1323 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1324 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1325
1326 if (i < 4)
1327 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1328 }
1329
1330 win_enable = 0x3f;
1331 win_protect = 0;
1332
1333 for (i = 0; i < dram->num_cs; i++) {
1334 const struct mbus_dram_window *cs = dram->cs + i;
1335 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
1336 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
1337
1338 mvreg_write(pp, MVNETA_WIN_SIZE(i),
1339 (cs->size - 1) & 0xffff0000);
1340
1341 win_enable &= ~(1 << i);
1342 win_protect |= 3 << (2 * i);
1343 }
1344
1345 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1346}
1347
1348/* Power up the port */
1349static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
1350{
1351 u32 ctrl;
1352
1353 /* MAC Cause register should be cleared */
1354 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
1355
1356 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1357
1358 /* Even though it might look weird, when we're configured in
1359 * SGMII or QSGMII mode, the RGMII bit needs to be set.
1360 */
1361 switch (phy_mode) {
1362 case PHY_INTERFACE_MODE_QSGMII:
1363 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
1364 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1365 break;
1366 case PHY_INTERFACE_MODE_SGMII:
1367 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
1368 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1369 break;
1370 case PHY_INTERFACE_MODE_RGMII:
1371 case PHY_INTERFACE_MODE_RGMII_ID:
1372 ctrl |= MVNETA_GMAC2_PORT_RGMII;
1373 break;
1374 default:
1375 return -EINVAL;
1376 }
1377
1378 /* Cancel Port Reset */
1379 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
1380 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
1381
1382 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
1383 MVNETA_GMAC2_PORT_RESET) != 0)
1384 continue;
1385
1386 return 0;
1387}
1388
1389/* Device initialization routine */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001390static int mvneta_init(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001391{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001392 struct eth_pdata *pdata = dev_get_platdata(dev);
1393 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001394 int err;
1395
1396 pp->tx_ring_size = MVNETA_MAX_TXD;
1397 pp->rx_ring_size = MVNETA_MAX_RXD;
1398
Stefan Roesee3b9c982015-11-19 07:46:15 +01001399 err = mvneta_init2(pp);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001400 if (err < 0) {
1401 dev_err(&pdev->dev, "can't init eth hal\n");
1402 return err;
1403 }
1404
Stefan Roesee3b9c982015-11-19 07:46:15 +01001405 mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001406
1407 err = mvneta_port_power_up(pp, pp->phy_interface);
1408 if (err < 0) {
1409 dev_err(&pdev->dev, "can't power up port\n");
1410 return err;
1411 }
1412
1413 /* Call open() now as it needs to be done before runing send() */
1414 mvneta_open(dev);
1415
1416 return 0;
1417}
1418
1419/* U-Boot only functions follow here */
1420
1421/* SMI / MDIO functions */
1422
1423static int smi_wait_ready(struct mvneta_port *pp)
1424{
1425 u32 timeout = MVNETA_SMI_TIMEOUT;
1426 u32 smi_reg;
1427
1428 /* wait till the SMI is not busy */
1429 do {
1430 /* read smi register */
1431 smi_reg = mvreg_read(pp, MVNETA_SMI);
1432 if (timeout-- == 0) {
1433 printf("Error: SMI busy timeout\n");
1434 return -EFAULT;
1435 }
1436 } while (smi_reg & MVNETA_SMI_BUSY);
1437
1438 return 0;
1439}
1440
1441/*
Stefan Roesee3b9c982015-11-19 07:46:15 +01001442 * mvneta_mdio_read - miiphy_read callback function.
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001443 *
1444 * Returns 16bit phy register value, or 0xffff on error
1445 */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001446static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001447{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001448 struct mvneta_port *pp = bus->priv;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001449 u32 smi_reg;
1450 u32 timeout;
1451
1452 /* check parameters */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001453 if (addr > MVNETA_PHY_ADDR_MASK) {
1454 printf("Error: Invalid PHY address %d\n", addr);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001455 return -EFAULT;
1456 }
1457
Stefan Roesee3b9c982015-11-19 07:46:15 +01001458 if (reg > MVNETA_PHY_REG_MASK) {
1459 printf("Err: Invalid register offset %d\n", reg);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001460 return -EFAULT;
1461 }
1462
1463 /* wait till the SMI is not busy */
1464 if (smi_wait_ready(pp) < 0)
1465 return -EFAULT;
1466
1467 /* fill the phy address and regiser offset and read opcode */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001468 smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1469 | (reg << MVNETA_SMI_REG_ADDR_OFFS)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001470 | MVNETA_SMI_OPCODE_READ;
1471
1472 /* write the smi register */
1473 mvreg_write(pp, MVNETA_SMI, smi_reg);
1474
Stefan Roesee3b9c982015-11-19 07:46:15 +01001475 /* wait till read value is ready */
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001476 timeout = MVNETA_SMI_TIMEOUT;
1477
1478 do {
1479 /* read smi register */
1480 smi_reg = mvreg_read(pp, MVNETA_SMI);
1481 if (timeout-- == 0) {
1482 printf("Err: SMI read ready timeout\n");
1483 return -EFAULT;
1484 }
1485 } while (!(smi_reg & MVNETA_SMI_READ_VALID));
1486
1487 /* Wait for the data to update in the SMI register */
1488 for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
1489 ;
1490
Stefan Roesee3b9c982015-11-19 07:46:15 +01001491 return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001492}
1493
1494/*
Stefan Roesee3b9c982015-11-19 07:46:15 +01001495 * mvneta_mdio_write - miiphy_write callback function.
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001496 *
1497 * Returns 0 if write succeed, -EINVAL on bad parameters
1498 * -ETIME on timeout
1499 */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001500static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
1501 u16 value)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001502{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001503 struct mvneta_port *pp = bus->priv;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001504 u32 smi_reg;
1505
1506 /* check parameters */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001507 if (addr > MVNETA_PHY_ADDR_MASK) {
1508 printf("Error: Invalid PHY address %d\n", addr);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001509 return -EFAULT;
1510 }
1511
Stefan Roesee3b9c982015-11-19 07:46:15 +01001512 if (reg > MVNETA_PHY_REG_MASK) {
1513 printf("Err: Invalid register offset %d\n", reg);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001514 return -EFAULT;
1515 }
1516
1517 /* wait till the SMI is not busy */
1518 if (smi_wait_ready(pp) < 0)
1519 return -EFAULT;
1520
1521 /* fill the phy addr and reg offset and write opcode and data */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001522 smi_reg = value << MVNETA_SMI_DATA_OFFS;
1523 smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
1524 | (reg << MVNETA_SMI_REG_ADDR_OFFS);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001525 smi_reg &= ~MVNETA_SMI_OPCODE_READ;
1526
1527 /* write the smi register */
1528 mvreg_write(pp, MVNETA_SMI, smi_reg);
1529
1530 return 0;
1531}
1532
Stefan Roesee3b9c982015-11-19 07:46:15 +01001533static int mvneta_start(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001534{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001535 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001536 struct phy_device *phydev;
1537
1538 mvneta_port_power_up(pp, pp->phy_interface);
1539
1540 if (!pp->init || pp->link == 0) {
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001541 if (mvneta_port_is_fixed_link(pp)) {
1542 u32 val;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001543
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001544 pp->init = 1;
1545 pp->link = 1;
1546 mvneta_init(dev);
1547
1548 val = MVNETA_GMAC_FORCE_LINK_UP |
1549 MVNETA_GMAC_IB_BYPASS_AN_EN |
1550 MVNETA_GMAC_SET_FC_EN |
1551 MVNETA_GMAC_ADVERT_FC_EN |
1552 MVNETA_GMAC_SAMPLE_TX_CFG_EN;
1553
1554 if (pp->duplex)
1555 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
1556
1557 if (pp->speed == SPEED_1000)
1558 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1559 else if (pp->speed == SPEED_100)
1560 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
1561
1562 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1563 } else {
1564 /* Set phy address of the port */
1565 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
1566
1567 phydev = phy_connect(pp->bus, pp->phyaddr, dev,
1568 pp->phy_interface);
Marek Behúncf2cf852018-04-24 17:21:29 +02001569 if (!phydev) {
1570 printf("phy_connect failed\n");
1571 return -ENODEV;
1572 }
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001573
1574 pp->phydev = phydev;
1575 phy_config(phydev);
1576 phy_startup(phydev);
1577 if (!phydev->link) {
1578 printf("%s: No link.\n", phydev->dev->name);
1579 return -1;
1580 }
1581
1582 /* Full init on first call */
1583 mvneta_init(dev);
1584 pp->init = 1;
1585 return 0;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001586 }
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001587 }
1588
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001589 /* Upon all following calls, this is enough */
1590 mvneta_port_up(pp);
1591 mvneta_port_enable(pp);
1592
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001593 return 0;
1594}
1595
Stefan Roesee3b9c982015-11-19 07:46:15 +01001596static int mvneta_send(struct udevice *dev, void *packet, int length)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001597{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001598 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001599 struct mvneta_tx_queue *txq = &pp->txqs[0];
1600 struct mvneta_tx_desc *tx_desc;
1601 int sent_desc;
1602 u32 timeout = 0;
1603
1604 /* Get a descriptor for the first part of the packet */
1605 tx_desc = mvneta_txq_next_desc_get(txq);
1606
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001607 tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
Stefan Roesee3b9c982015-11-19 07:46:15 +01001608 tx_desc->data_size = length;
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001609 flush_dcache_range((ulong)packet,
1610 (ulong)packet + ALIGN(length, PKTALIGN));
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001611
1612 /* First and Last descriptor */
1613 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
1614 mvneta_txq_pend_desc_add(pp, txq, 1);
1615
1616 /* Wait for packet to be sent (queue might help with speed here) */
1617 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1618 while (!sent_desc) {
1619 if (timeout++ > 10000) {
1620 printf("timeout: packet not sent\n");
1621 return -1;
1622 }
1623 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1624 }
1625
1626 /* txDone has increased - hw sent packet */
1627 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001628
1629 return 0;
1630}
1631
Stefan Roesee3b9c982015-11-19 07:46:15 +01001632static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001633{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001634 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001635 int rx_done;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001636 struct mvneta_rx_queue *rxq;
Stefan Roesee3b9c982015-11-19 07:46:15 +01001637 int rx_bytes = 0;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001638
1639 /* get rx queue */
1640 rxq = mvneta_rxq_handle_get(pp, rxq_def);
1641 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001642
Stefan Roesee3b9c982015-11-19 07:46:15 +01001643 if (rx_done) {
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001644 struct mvneta_rx_desc *rx_desc;
1645 unsigned char *data;
1646 u32 rx_status;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001647
1648 /*
1649 * No cache invalidation needed here, since the desc's are
1650 * located in a uncached memory region
1651 */
1652 rx_desc = mvneta_rxq_next_desc_get(rxq);
1653
1654 rx_status = rx_desc->status;
1655 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1656 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1657 mvneta_rx_error(pp, rx_desc);
1658 /* leave the descriptor untouched */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001659 return -EIO;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001660 }
1661
1662 /* 2 bytes for marvell header. 4 bytes for crc */
1663 rx_bytes = rx_desc->data_size - 6;
1664
1665 /* give packet to stack - skip on first 2 bytes */
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001666 data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001667 /*
1668 * No cache invalidation needed here, since the rx_buffer's are
1669 * located in a uncached memory region
1670 */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001671 *packetp = data;
1672
Jason Brown32ac8b02017-11-28 11:12:43 -08001673 /*
1674 * Only mark one descriptor as free
1675 * since only one was processed
1676 */
1677 mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001678 }
1679
Stefan Roesee3b9c982015-11-19 07:46:15 +01001680 return rx_bytes;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001681}
1682
Stefan Roesee3b9c982015-11-19 07:46:15 +01001683static int mvneta_probe(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001684{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001685 struct eth_pdata *pdata = dev_get_platdata(dev);
1686 struct mvneta_port *pp = dev_get_priv(dev);
1687 void *blob = (void *)gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -07001688 int node = dev_of_offset(dev);
Stefan Roesee3b9c982015-11-19 07:46:15 +01001689 struct mii_dev *bus;
1690 unsigned long addr;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001691 void *bd_space;
Konstantin Porotchkin976feda2017-02-16 13:52:27 +02001692 int ret;
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001693 int fl_node;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001694
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001695 /*
1696 * Allocate buffer area for descs and rx_buffers. This is only
1697 * done once for all interfaces. As only one interface can
Chris Packham6723b232016-08-29 20:54:02 +12001698 * be active. Make this area DMA safe by disabling the D-cache
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001699 */
1700 if (!buffer_loc.tx_descs) {
Jon Nettleton199b27b2018-05-30 08:52:29 +03001701 u32 size;
1702
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001703 /* Align buffer area for descs and rx_buffers to 1MiB */
1704 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
Rabeeh Khoury0f8888b2018-06-19 21:36:50 +03001705 flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE);
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001706 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001707 DCACHE_OFF);
1708 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
Jon Nettleton199b27b2018-05-30 08:52:29 +03001709 size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc),
1710 ARCH_DMA_MINALIGN);
Rabeeh Khoury318b5d72018-06-19 21:36:51 +03001711 memset(buffer_loc.tx_descs, 0, size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001712 buffer_loc.rx_descs = (struct mvneta_rx_desc *)
Jon Nettleton199b27b2018-05-30 08:52:29 +03001713 ((phys_addr_t)bd_space + size);
1714 size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc),
1715 ARCH_DMA_MINALIGN);
1716 buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001717 }
1718
Stefan Roesee3b9c982015-11-19 07:46:15 +01001719 pp->base = (void __iomem *)pdata->iobase;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001720
Stefan Roesee3b9c982015-11-19 07:46:15 +01001721 /* Configure MBUS address windows */
Simon Glass911f3ae2017-05-18 20:08:57 -06001722 if (device_is_compatible(dev, "marvell,armada-3700-neta"))
Stefan Roese544eefe2016-05-19 17:46:36 +02001723 mvneta_bypass_mbus_windows(pp);
1724 else
1725 mvneta_conf_mbus_windows(pp);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001726
Stefan Roesee3b9c982015-11-19 07:46:15 +01001727 /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
1728 pp->phy_interface = pdata->phy_interface;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001729
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001730 /* fetch 'fixed-link' property from 'neta' node */
1731 fl_node = fdt_subnode_offset(blob, node, "fixed-link");
1732 if (fl_node != -FDT_ERR_NOTFOUND) {
1733 /* set phy_addr to invalid value for fixed link */
1734 pp->phyaddr = PHY_MAX_ADDR + 1;
1735 pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
1736 pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
1737 } else {
1738 /* Now read phyaddr from DT */
1739 addr = fdtdec_get_int(blob, node, "phy", 0);
1740 addr = fdt_node_offset_by_phandle(blob, addr);
1741 pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
1742 }
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001743
Stefan Roesee3b9c982015-11-19 07:46:15 +01001744 bus = mdio_alloc();
1745 if (!bus) {
1746 printf("Failed to allocate MDIO bus\n");
1747 return -ENOMEM;
1748 }
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001749
Stefan Roesee3b9c982015-11-19 07:46:15 +01001750 bus->read = mvneta_mdio_read;
1751 bus->write = mvneta_mdio_write;
1752 snprintf(bus->name, sizeof(bus->name), dev->name);
1753 bus->priv = (void *)pp;
1754 pp->bus = bus;
1755
Konstantin Porotchkin976feda2017-02-16 13:52:27 +02001756 ret = mdio_register(bus);
1757 if (ret)
1758 return ret;
1759
1760 return board_network_enable(bus);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001761}
Stefan Roesee3b9c982015-11-19 07:46:15 +01001762
1763static void mvneta_stop(struct udevice *dev)
1764{
1765 struct mvneta_port *pp = dev_get_priv(dev);
1766
1767 mvneta_port_down(pp);
1768 mvneta_port_disable(pp);
1769}
1770
1771static const struct eth_ops mvneta_ops = {
1772 .start = mvneta_start,
1773 .send = mvneta_send,
1774 .recv = mvneta_recv,
1775 .stop = mvneta_stop,
Matt Pelland0a85f022018-03-27 13:18:25 -04001776 .write_hwaddr = mvneta_write_hwaddr,
Stefan Roesee3b9c982015-11-19 07:46:15 +01001777};
1778
1779static int mvneta_ofdata_to_platdata(struct udevice *dev)
1780{
1781 struct eth_pdata *pdata = dev_get_platdata(dev);
1782 const char *phy_mode;
1783
Simon Glassa821c4a2017-05-17 17:18:05 -06001784 pdata->iobase = devfdt_get_addr(dev);
Stefan Roesee3b9c982015-11-19 07:46:15 +01001785
1786 /* Get phy-mode / phy_interface from DT */
1787 pdata->phy_interface = -1;
Simon Glasse160f7d2017-01-17 16:52:55 -07001788 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1789 NULL);
Stefan Roesee3b9c982015-11-19 07:46:15 +01001790 if (phy_mode)
1791 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1792 if (pdata->phy_interface == -1) {
1793 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1794 return -EINVAL;
1795 }
1796
1797 return 0;
1798}
1799
1800static const struct udevice_id mvneta_ids[] = {
1801 { .compatible = "marvell,armada-370-neta" },
1802 { .compatible = "marvell,armada-xp-neta" },
Stefan Roese544eefe2016-05-19 17:46:36 +02001803 { .compatible = "marvell,armada-3700-neta" },
Stefan Roesee3b9c982015-11-19 07:46:15 +01001804 { }
1805};
1806
1807U_BOOT_DRIVER(mvneta) = {
1808 .name = "mvneta",
1809 .id = UCLASS_ETH,
1810 .of_match = mvneta_ids,
1811 .ofdata_to_platdata = mvneta_ofdata_to_platdata,
1812 .probe = mvneta_probe,
1813 .ops = &mvneta_ops,
1814 .priv_auto_alloc_size = sizeof(struct mvneta_port),
1815 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1816};