Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __FM_H__ |
| 7 | #define __FM_H__ |
| 8 | |
| 9 | #include <common.h> |
Claudiu Manoil | 93f26f1 | 2014-09-05 13:52:36 +0800 | [diff] [blame] | 10 | #include <phy.h> |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 11 | #include <fm_eth.h> |
Shaohui Xie | 8225b2f | 2015-10-26 19:47:47 +0800 | [diff] [blame] | 12 | #include <fsl_fman.h> |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 13 | |
| 14 | /* Port ID */ |
| 15 | #define OH_PORT_ID_BASE 0x01 |
| 16 | #define MAX_NUM_OH_PORT 7 |
| 17 | #define RX_PORT_1G_BASE 0x08 |
Tom Rini | cdc5ed8 | 2022-11-16 13:10:29 -0500 | [diff] [blame] | 18 | #define MAX_NUM_RX_PORT_1G CFG_SYS_NUM_FM1_DTSEC |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 19 | #define RX_PORT_10G_BASE 0x10 |
Shengzhou Liu | 82a55c1 | 2013-11-22 17:39:09 +0800 | [diff] [blame] | 20 | #define RX_PORT_10G_BASE2 0x08 |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 21 | #define TX_PORT_1G_BASE 0x28 |
Tom Rini | cdc5ed8 | 2022-11-16 13:10:29 -0500 | [diff] [blame] | 22 | #define MAX_NUM_TX_PORT_1G CFG_SYS_NUM_FM1_DTSEC |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 23 | #define TX_PORT_10G_BASE 0x30 |
Shengzhou Liu | 82a55c1 | 2013-11-22 17:39:09 +0800 | [diff] [blame] | 24 | #define TX_PORT_10G_BASE2 0x28 |
Zhao Qiang | ffee1dd | 2013-09-04 10:11:27 +0800 | [diff] [blame] | 25 | #define MIIM_TIMEOUT 0xFFFF |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 26 | |
| 27 | struct fm_muram { |
Hou Zhiqiang | 9fc29db | 2015-10-26 19:47:44 +0800 | [diff] [blame] | 28 | void *base; |
| 29 | void *top; |
| 30 | size_t size; |
| 31 | void *alloc; |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 32 | }; |
| 33 | #define FM_MURAM_RES_SIZE 0x01000 |
| 34 | |
| 35 | /* Rx/Tx buffer descriptor */ |
| 36 | struct fm_port_bd { |
| 37 | u16 status; |
| 38 | u16 len; |
| 39 | u32 res0; |
| 40 | u16 res1; |
| 41 | u16 buf_ptr_hi; |
| 42 | u32 buf_ptr_lo; |
| 43 | }; |
| 44 | |
| 45 | /* Common BD flags */ |
| 46 | #define BD_LAST 0x0800 |
| 47 | |
| 48 | /* Rx BD status flags */ |
| 49 | #define RxBD_EMPTY 0x8000 |
| 50 | #define RxBD_LAST BD_LAST |
| 51 | #define RxBD_FIRST 0x0400 |
| 52 | #define RxBD_PHYS_ERR 0x0008 |
| 53 | #define RxBD_SIZE_ERR 0x0004 |
| 54 | #define RxBD_ERROR (RxBD_PHYS_ERR | RxBD_SIZE_ERR) |
| 55 | |
| 56 | /* Tx BD status flags */ |
| 57 | #define TxBD_READY 0x8000 |
| 58 | #define TxBD_LAST BD_LAST |
| 59 | |
Madalin Bucur | 6eb32a0 | 2020-04-23 16:25:19 +0300 | [diff] [blame] | 60 | enum fm_mac_type { |
| 61 | #ifdef CONFIG_SYS_FMAN_V3 |
| 62 | FM_MEMAC, |
| 63 | #else |
| 64 | FM_DTSEC, |
| 65 | FM_TGEC, |
| 66 | #endif |
| 67 | }; |
Madalin Bucur | 6eb32a0 | 2020-04-23 16:25:19 +0300 | [diff] [blame] | 68 | |
| 69 | /* Fman ethernet private struct */ |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 70 | /* Rx/Tx queue descriptor */ |
| 71 | struct fm_port_qd { |
| 72 | u16 gen; |
| 73 | u16 bd_ring_base_hi; |
| 74 | u32 bd_ring_base_lo; |
| 75 | u16 bd_ring_size; |
| 76 | u16 offset_in; |
| 77 | u16 offset_out; |
| 78 | u16 res0; |
| 79 | u32 res1[0x4]; |
| 80 | }; |
| 81 | |
| 82 | /* IM global parameter RAM */ |
| 83 | struct fm_port_global_pram { |
| 84 | u32 mode; /* independent mode register */ |
| 85 | u32 rxqd_ptr; /* Rx queue descriptor pointer */ |
| 86 | u32 txqd_ptr; /* Tx queue descriptor pointer */ |
| 87 | u16 mrblr; /* max Rx buffer length */ |
| 88 | u16 rxqd_bsy_cnt; /* RxQD busy counter, should be cleared */ |
| 89 | u32 res0[0x4]; |
| 90 | struct fm_port_qd rxqd; /* Rx queue descriptor */ |
| 91 | struct fm_port_qd txqd; /* Tx queue descriptor */ |
| 92 | u32 res1[0x28]; |
| 93 | }; |
| 94 | |
| 95 | #define FM_PRAM_SIZE sizeof(struct fm_port_global_pram) |
| 96 | #define FM_PRAM_ALIGN 256 |
| 97 | #define PRAM_MODE_GLOBAL 0x20000000 |
| 98 | #define PRAM_MODE_GRACEFUL_STOP 0x00800000 |
| 99 | |
York Sun | 41c7b7b | 2016-11-16 16:06:48 -0800 | [diff] [blame] | 100 | #if defined(CONFIG_ARCH_P1023) |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 101 | #define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */ |
| 102 | #else |
| 103 | #define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */ |
| 104 | #endif |
| 105 | #define FM_FREE_POOL_ALIGN 256 |
| 106 | |
Hou Zhiqiang | 9fc29db | 2015-10-26 19:47:44 +0800 | [diff] [blame] | 107 | void *fm_muram_alloc(int fm_idx, size_t size, ulong align); |
| 108 | void *fm_muram_base(int fm_idx); |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 109 | int fm_init_common(int index, struct ccsr_fman *reg); |
| 110 | int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info); |
| 111 | phy_interface_t fman_port_enet_if(enum fm_port port); |
Kumar Gala | 69a8524 | 2011-09-14 12:01:35 -0500 | [diff] [blame] | 112 | void fman_disable_port(enum fm_port port); |
Valentin Longchamp | f51d3b7 | 2013-10-18 11:47:21 +0200 | [diff] [blame] | 113 | void fman_enable_port(enum fm_port port); |
Madalin Bucur | 6eb32a0 | 2020-04-23 16:25:19 +0300 | [diff] [blame] | 114 | int fman_id(struct udevice *dev); |
| 115 | void *fman_port(struct udevice *dev, int num); |
Madalin Bucur | 6eb32a0 | 2020-04-23 16:25:19 +0300 | [diff] [blame] | 116 | void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num); |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 117 | |
| 118 | struct fsl_enet_mac { |
| 119 | void *base; /* MAC controller registers base address */ |
| 120 | void *phyregs; |
| 121 | int max_rx_len; |
| 122 | void (*init_mac)(struct fsl_enet_mac *mac); |
| 123 | void (*enable_mac)(struct fsl_enet_mac *mac); |
| 124 | void (*disable_mac)(struct fsl_enet_mac *mac); |
| 125 | void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr); |
| 126 | void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type, |
| 127 | int speed); |
| 128 | }; |
| 129 | |
| 130 | /* Fman ethernet private struct */ |
| 131 | struct fm_eth { |
| 132 | int fm_index; /* Fman index */ |
| 133 | u32 num; /* 0..n-1 for give type */ |
| 134 | struct fm_bmi_tx_port *tx_port; |
| 135 | struct fm_bmi_rx_port *rx_port; |
| 136 | enum fm_eth_type type; /* 1G or 10G ethernet */ |
| 137 | phy_interface_t enet_if; |
| 138 | struct fsl_enet_mac *mac; /* MAC controller */ |
| 139 | struct mii_dev *bus; |
| 140 | struct phy_device *phydev; |
| 141 | int phyaddr; |
Madalin Bucur | 6eb32a0 | 2020-04-23 16:25:19 +0300 | [diff] [blame] | 142 | enum fm_mac_type mac_type; |
| 143 | struct udevice *dev; |
| 144 | struct udevice *pcs_mdio; |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 145 | int max_rx_len; |
| 146 | struct fm_port_global_pram *rx_pram; /* Rx parameter table */ |
| 147 | struct fm_port_global_pram *tx_pram; /* Tx parameter table */ |
| 148 | void *rx_bd_ring; /* Rx BD ring base */ |
| 149 | void *cur_rxbd; /* current Rx BD */ |
| 150 | void *rx_buf; /* Rx buffer base */ |
| 151 | void *tx_bd_ring; /* Tx BD ring base */ |
| 152 | void *cur_txbd; /* current Tx BD */ |
| 153 | }; |
| 154 | |
| 155 | #define RX_BD_RING_SIZE 8 |
| 156 | #define TX_BD_RING_SIZE 8 |
| 157 | #define MAX_RXBUF_LOG2 11 |
| 158 | #define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2) |
| 159 | |
Rotariu Marian-Cristian | 1155d8d | 2014-05-19 10:59:52 +0300 | [diff] [blame] | 160 | #define PORT_IS_ENABLED(port) (fm_port_to_index(port) == -1 ? \ |
| 161 | 0 : fm_info[fm_port_to_index(port)].enabled) |
Shengzhou Liu | ae8a5d1 | 2013-03-25 07:39:29 +0000 | [diff] [blame] | 162 | |
Kumar Gala | c916d7c | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 163 | #endif /* __FM_H__ */ |