blob: 9eff423acd12ad77f05c7e02d214b707b4bb672e [file] [log] [blame]
Simon Glass1b2fd5b2015-09-01 19:19:37 -06001/*
2 * spi driver for rockchip
3 *
4 * (C) Copyright 2015 Google, Inc
5 *
6 * (C) Copyright 2008-2013 Rockchip Electronics
7 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12#include <common.h>
13#include <clk.h>
14#include <dm.h>
15#include <errno.h>
16#include <spi.h>
17#include <asm/errno.h>
18#include <asm/io.h>
19#include <asm/arch/clock.h>
20#include <asm/arch/periph.h>
21#include <dm/pinctrl.h>
22#include "rk_spi.h"
23
24DECLARE_GLOBAL_DATA_PTR;
25
26/* Change to 1 to output registers at the start of each transaction */
27#define DEBUG_RK_SPI 0
28
29struct rockchip_spi_platdata {
Simon Glass1b2fd5b2015-09-01 19:19:37 -060030 s32 frequency; /* Default clock frequency, -1 for none */
31 fdt_addr_t base;
32 uint deactivate_delay_us; /* Delay to wait after deactivate */
Simon Glass183a3a02016-01-21 19:44:10 -070033 uint activate_delay_us; /* Delay to wait after activate */
Simon Glass1b2fd5b2015-09-01 19:19:37 -060034};
35
36struct rockchip_spi_priv {
37 struct rockchip_spi *regs;
Simon Glass71037d12016-01-21 19:43:43 -070038 struct udevice *clk;
39 int clk_id;
Simon Glass1b2fd5b2015-09-01 19:19:37 -060040 unsigned int max_freq;
41 unsigned int mode;
Simon Glass1b2fd5b2015-09-01 19:19:37 -060042 ulong last_transaction_us; /* Time of last transaction end */
43 u8 bits_per_word; /* max 16 bits per word */
44 u8 n_bytes;
45 unsigned int speed_hz;
Simon Glass28a943c2016-01-21 19:44:03 -070046 unsigned int last_speed_hz;
Simon Glass1b2fd5b2015-09-01 19:19:37 -060047 unsigned int tmode;
48 uint input_rate;
49};
50
51#define SPI_FIFO_DEPTH 32
52
53static void rkspi_dump_regs(struct rockchip_spi *regs)
54{
55 debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
56 debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
57 debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
58 debug("ser: \t\t0x%08x\n", readl(&regs->ser));
59 debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
60 debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
61 debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
62 debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
63 debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
64 debug("sr: \t\t0x%08x\n", readl(&regs->sr));
65 debug("imr: \t\t0x%08x\n", readl(&regs->imr));
66 debug("isr: \t\t0x%08x\n", readl(&regs->isr));
67 debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
68 debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
69 debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
70}
71
72static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
73{
74 writel(enable ? 1 : 0, &regs->enr);
75}
76
77static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
78{
79 uint clk_div;
80
81 clk_div = clk_get_divisor(priv->input_rate, speed);
82 debug("spi speed %u, div %u\n", speed, clk_div);
83
84 writel(clk_div, &priv->regs->baudr);
Simon Glass28a943c2016-01-21 19:44:03 -070085 priv->last_speed_hz = speed;
Simon Glass1b2fd5b2015-09-01 19:19:37 -060086}
87
88static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
89{
90 unsigned long start;
91
92 start = get_timer(0);
93 while (readl(&regs->sr) & SR_BUSY) {
94 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
95 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
96 return -ETIMEDOUT;
97 }
98 }
99
100 return 0;
101}
102
Simon Glass183a3a02016-01-21 19:44:10 -0700103static void spi_cs_activate(struct udevice *dev, uint cs)
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600104{
Simon Glass183a3a02016-01-21 19:44:10 -0700105 struct udevice *bus = dev->parent;
106 struct rockchip_spi_platdata *plat = bus->platdata;
107 struct rockchip_spi_priv *priv = dev_get_priv(bus);
108 struct rockchip_spi *regs = priv->regs;
109
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600110 debug("activate cs%u\n", cs);
111 writel(1 << cs, &regs->ser);
Simon Glass183a3a02016-01-21 19:44:10 -0700112 if (plat->activate_delay_us)
113 udelay(plat->activate_delay_us);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600114}
115
Simon Glass183a3a02016-01-21 19:44:10 -0700116static void spi_cs_deactivate(struct udevice *dev, uint cs)
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600117{
Simon Glass183a3a02016-01-21 19:44:10 -0700118 struct udevice *bus = dev->parent;
119 struct rockchip_spi_platdata *plat = bus->platdata;
120 struct rockchip_spi_priv *priv = dev_get_priv(bus);
121 struct rockchip_spi *regs = priv->regs;
122
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600123 debug("deactivate cs%u\n", cs);
124 writel(0, &regs->ser);
Simon Glass183a3a02016-01-21 19:44:10 -0700125
126 /* Remember time of this transaction so we can honour the bus delay */
127 if (plat->deactivate_delay_us)
128 priv->last_transaction_us = timer_get_us();
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600129}
130
131static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
132{
133 struct rockchip_spi_platdata *plat = bus->platdata;
Simon Glass71037d12016-01-21 19:43:43 -0700134 struct rockchip_spi_priv *priv = dev_get_priv(bus);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600135 const void *blob = gd->fdt_blob;
136 int node = bus->of_offset;
137 int ret;
138
139 plat->base = dev_get_addr(bus);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600140
Simon Glass71037d12016-01-21 19:43:43 -0700141 ret = clk_get_by_index(bus, 0, &priv->clk);
142 if (ret < 0) {
143 debug("%s: Could not get clock for %s: %d\n", __func__,
144 bus->name, ret);
145 return ret;
146 }
147 priv->clk_id = ret;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600148
149 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
Simon Glass71037d12016-01-21 19:43:43 -0700150 50000000);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600151 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
152 "spi-deactivate-delay", 0);
Simon Glass183a3a02016-01-21 19:44:10 -0700153 plat->activate_delay_us = fdtdec_get_int(blob, node,
154 "spi-activate-delay", 0);
Simon Glass90a28472016-01-21 19:44:12 -0700155 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
156 __func__, (uint)plat->base, plat->frequency,
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600157 plat->deactivate_delay_us);
158
159 return 0;
160}
161
162static int rockchip_spi_probe(struct udevice *bus)
163{
164 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
165 struct rockchip_spi_priv *priv = dev_get_priv(bus);
166 int ret;
167
168 debug("%s: probe\n", __func__);
169 priv->regs = (struct rockchip_spi *)plat->base;
170
171 priv->last_transaction_us = timer_get_us();
172 priv->max_freq = plat->frequency;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600173
174 /*
175 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
176 * is the assumed speed for CLK_GENERAL.
177 */
Simon Glass71037d12016-01-21 19:43:43 -0700178 ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600179 if (ret < 0) {
180 debug("%s: Failed to set clock: %d\n", __func__, ret);
181 return ret;
182 }
183 priv->input_rate = ret;
184 debug("%s: rate = %u\n", __func__, priv->input_rate);
185 priv->bits_per_word = 8;
186 priv->tmode = TMOD_TR; /* Tx & Rx */
187
188 return 0;
189}
190
191static int rockchip_spi_claim_bus(struct udevice *dev)
192{
193 struct udevice *bus = dev->parent;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600194 struct rockchip_spi_priv *priv = dev_get_priv(bus);
195 struct rockchip_spi *regs = priv->regs;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600196 u8 spi_dfs, spi_tf;
197 uint ctrlr0;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600198
199 /* Disable the SPI hardware */
200 rkspi_enable_chip(regs, 0);
201
202 switch (priv->bits_per_word) {
203 case 8:
204 priv->n_bytes = 1;
205 spi_dfs = DFS_8BIT;
206 spi_tf = HALF_WORD_OFF;
207 break;
208 case 16:
209 priv->n_bytes = 2;
210 spi_dfs = DFS_16BIT;
211 spi_tf = HALF_WORD_ON;
212 break;
213 default:
214 debug("%s: unsupported bits: %dbits\n", __func__,
215 priv->bits_per_word);
216 return -EPROTONOSUPPORT;
217 }
218
Simon Glass28a943c2016-01-21 19:44:03 -0700219 if (priv->speed_hz != priv->last_speed_hz)
220 rkspi_set_clk(priv, priv->speed_hz);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600221
222 /* Operation Mode */
223 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
224
225 /* Data Frame Size */
Simon Glass2b9fe112016-01-21 19:44:04 -0700226 ctrlr0 |= spi_dfs << DFS_SHIFT;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600227
228 /* set SPI mode 0..3 */
229 if (priv->mode & SPI_CPOL)
230 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
231 if (priv->mode & SPI_CPHA)
232 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
233
234 /* Chip Select Mode */
235 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
236
237 /* SSN to Sclk_out delay */
238 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
239
240 /* Serial Endian Mode */
241 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
242
243 /* First Bit Mode */
244 ctrlr0 |= FBM_MSB << FBM_SHIFT;
245
246 /* Byte and Halfword Transform */
Simon Glass2b9fe112016-01-21 19:44:04 -0700247 ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600248
249 /* Rxd Sample Delay */
250 ctrlr0 |= 0 << RXDSD_SHIFT;
251
252 /* Frame Format */
253 ctrlr0 |= FRF_SPI << FRF_SHIFT;
254
255 /* Tx and Rx mode */
256 ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
257
258 writel(ctrlr0, &regs->ctrlr0);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600259
260 return 0;
261}
262
263static int rockchip_spi_release_bus(struct udevice *dev)
264{
Simon Glasse15af8e2016-01-21 19:44:11 -0700265 struct udevice *bus = dev->parent;
266 struct rockchip_spi_priv *priv = dev_get_priv(bus);
267
268 rkspi_enable_chip(priv->regs, false);
269
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600270 return 0;
271}
272
273static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
274 const void *dout, void *din, unsigned long flags)
275{
276 struct udevice *bus = dev->parent;
277 struct rockchip_spi_priv *priv = dev_get_priv(bus);
278 struct rockchip_spi *regs = priv->regs;
279 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
280 int len = bitlen >> 3;
281 const u8 *out = dout;
282 u8 *in = din;
283 int toread, towrite;
284 int ret;
285
286 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
287 len, flags);
288 if (DEBUG_RK_SPI)
289 rkspi_dump_regs(regs);
290
291 /* Assert CS before transfer */
292 if (flags & SPI_XFER_BEGIN)
Simon Glass183a3a02016-01-21 19:44:10 -0700293 spi_cs_activate(dev, slave_plat->cs);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600294
295 while (len > 0) {
296 int todo = min(len, 0xffff);
297
Simon Glasse15af8e2016-01-21 19:44:11 -0700298 rkspi_enable_chip(regs, false);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600299 writel(todo - 1, &regs->ctrlr1);
300 rkspi_enable_chip(regs, true);
301
302 toread = todo;
303 towrite = todo;
304 while (toread || towrite) {
305 u32 status = readl(&regs->sr);
306
307 if (towrite && !(status & SR_TF_FULL)) {
308 writel(out ? *out++ : 0, regs->txdr);
309 towrite--;
310 }
311 if (toread && !(status & SR_RF_EMPT)) {
312 u32 byte = readl(regs->rxdr);
313
314 if (in)
315 *in++ = byte;
316 toread--;
317 }
318 }
319 ret = rkspi_wait_till_not_busy(regs);
320 if (ret)
321 break;
322 len -= todo;
323 }
324
325 /* Deassert CS after transfer */
326 if (flags & SPI_XFER_END)
Simon Glass183a3a02016-01-21 19:44:10 -0700327 spi_cs_deactivate(dev, slave_plat->cs);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600328
329 rkspi_enable_chip(regs, false);
330
331 return ret;
332}
333
334static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
335{
336 struct rockchip_spi_priv *priv = dev_get_priv(bus);
337
338 if (speed > ROCKCHIP_SPI_MAX_RATE)
339 return -EINVAL;
340 if (speed > priv->max_freq)
341 speed = priv->max_freq;
342 priv->speed_hz = speed;
343
344 return 0;
345}
346
347static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
348{
349 struct rockchip_spi_priv *priv = dev_get_priv(bus);
350
351 priv->mode = mode;
352
353 return 0;
354}
355
356static const struct dm_spi_ops rockchip_spi_ops = {
357 .claim_bus = rockchip_spi_claim_bus,
358 .release_bus = rockchip_spi_release_bus,
359 .xfer = rockchip_spi_xfer,
360 .set_speed = rockchip_spi_set_speed,
361 .set_mode = rockchip_spi_set_mode,
362 /*
363 * cs_info is not needed, since we require all chip selects to be
364 * in the device tree explicitly
365 */
366};
367
368static const struct udevice_id rockchip_spi_ids[] = {
369 { .compatible = "rockchip,rk3288-spi" },
370 { }
371};
372
373U_BOOT_DRIVER(rockchip_spi) = {
374 .name = "rockchip_spi",
375 .id = UCLASS_SPI,
376 .of_match = rockchip_spi_ids,
377 .ops = &rockchip_spi_ops,
378 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
379 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
380 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
381 .probe = rockchip_spi_probe,
382};