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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 46947ef68f6a10352fce148da33521f1d2df37cb / . / board / logicpd / am3517evm / am3517evm.h
blob: 283b4535a6be0d41b3030e5b6bf53280f3f7c550 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]2/*
3 * am3517evm.h - Header file for the AM3517 EVM.
4 *
5 * Author: Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * Based on ti/evm/evm.h
8 *
9 * Copyright (C) 2010
Nishanth Menona94a4072023-11-01 15:56:03 -0500[diff] [blame]10 * Texas Instruments Incorporated - https://www.ti.com/
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]11 */
12
13#ifndef _AM3517EVM_H_
14#define _AM3517EVM_H_
15
16const omap3_sysinfo sysinfo = {
17 DDR_DISCRETE,
18 "AM3517EVM Board",
19 "NAND",
20};
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]21
22/*
23 * IEN - Input Enable
24 * IDIS - Input Disable
25 * PTD - Pull type Down
26 * PTU - Pull type Up
27 * DIS - Pull type selection is inactive
28 * EN - Pull type selection is active
29 * M0 - Mode 0
30 * The commented string gives the final mux configuration for that pin
31 */
32#define MUX_AM3517EVM() \
33 /* SDRC */\
34 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
35 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
36 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
37 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
38 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
39 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
40 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
41 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
42 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
43 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
44 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
45 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
46 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
47 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
48 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
49 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
50 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
51 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
52 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
53 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
54 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
55 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
56 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
57 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
58 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
59 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
60 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
61 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
62 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
63 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
64 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
65 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
66 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
67 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
68 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
69 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
70 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
71 MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
72 MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
73 MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
74 MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
75 MUX_VAL(CP(SDRC_CKE0), (M0)) \
76 MUX_VAL(CP(SDRC_CKE1), (M0)) \
77 /*sdrc_strben_dly0*/\
78 MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
79 /*sdrc_strben_dly1*/\
80 MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
81 /* GPMC */\
82 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
83 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
84 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
85 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
86 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
87 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
88 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
89 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
90 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
91 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
92 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
93 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
94 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
95 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
96 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
97 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
98 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
99 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
100 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
101 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
102 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
103 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
104 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
105 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
106 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
107 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
108 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
109 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
110 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
111 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
112 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
113 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
Adam Ford02acbb92019-07-01 09:33:39 -0500[diff] [blame]114 MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) \
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]115 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \
116 MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
117 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
118 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
119 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
120 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
121 MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
122 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
123 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
124 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]125 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]126 /* MMC */\
127 MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
128 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
129 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
130 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
131 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
132 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]133 /* UART */\
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]134 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
135 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
136 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
137 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]138 /* Control and debug */\
139 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
140 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
141 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]142 MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
143 MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
144 \
145 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
146 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
147 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
148 /* JTAG */\
Igor Grinbergb5ff2052014-10-21 18:25:30 +0300[diff] [blame]149 MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]150 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
151 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
152 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
153 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
154 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
155 /* ETK (ES2 onwards) */\
Vaibhav Hiremathed01e452010-06-07 15:20:43 -0400[diff] [blame]156 MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
157 MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
158 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
159 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \
160 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \
161 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \
162 /* Die to Die */\
163 MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
164 MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
165 MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
166 MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
167 MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
168 MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
169 MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
170 MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
171 MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
172 MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
173 MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
174 MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
175 MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
176 MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
177 MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
178 MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
179 MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
180 MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
181 MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
182 MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
183 MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
184 MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
185 MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
186 MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
187 MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
188 MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
189 MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
190 MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
191 MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
192 MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
193
194#endif