blob: e6f53f91e63a5eedf3cad1764d5f1d6696db6668 [file] [log] [blame]
Ian Campbell643cf0e2014-05-05 11:52:23 +01001/*
2 * (C) Copyright 2007-2012
3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4 * Tom Cubie <tangliang@allwinnertech.com>
5 *
6 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12#include <asm/io.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/gpio.h>
Hans de Goedea93b0fe2016-03-16 20:57:28 +010015#include <asm/arch/prcm.h>
Philipp Tomsichea1af9f2016-10-28 18:21:29 +080016#include <asm/arch/gtbus.h>
Ian Campbell643cf0e2014-05-05 11:52:23 +010017#include <asm/arch/sys_proto.h>
18
Chen-Yu Tsaied805842016-01-06 15:13:07 +080019__weak void clock_init_sec(void)
20{
21}
22
Philipp Tomsichea1af9f2016-10-28 18:21:29 +080023__weak void gtbus_init(void)
24{
25}
26
Ian Campbell643cf0e2014-05-05 11:52:23 +010027int clock_init(void)
28{
29#ifdef CONFIG_SPL_BUILD
30 clock_init_safe();
Philipp Tomsichea1af9f2016-10-28 18:21:29 +080031 gtbus_init();
Ian Campbell643cf0e2014-05-05 11:52:23 +010032#endif
33 clock_init_uart();
Chen-Yu Tsaied805842016-01-06 15:13:07 +080034 clock_init_sec();
Ian Campbell643cf0e2014-05-05 11:52:23 +010035
36 return 0;
37}
Hans de Goedea93b0fe2016-03-16 20:57:28 +010038
39/* These functions are shared between various SoCs so put them here. */
40#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
41int clock_twi_onoff(int port, int state)
42{
43 struct sunxi_ccm_reg *const ccm =
44 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
45
46 if (port == 5) {
47 if (state)
48 prcm_apb0_enable(
49 PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
50 else
51 prcm_apb0_disable(
52 PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
53 return 0;
54 }
55
56 /* set the apb clock gate and reset for twi */
57 if (state) {
58 setbits_le32(&ccm->apb2_gate,
59 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
60 setbits_le32(&ccm->apb2_reset_cfg,
61 1 << (APB2_RESET_TWI_SHIFT + port));
62 } else {
63 clrbits_le32(&ccm->apb2_reset_cfg,
64 1 << (APB2_RESET_TWI_SHIFT + port));
65 clrbits_le32(&ccm->apb2_gate,
66 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
67 }
68
69 return 0;
70}
71#endif