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Jean-Christophe PLAGNIOL-VILLARDc8aa7df2008-10-31 12:26:55 +01001#
2# (C) Copyright 2008
3# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4#
Wolfgang Denk1a459662013-07-08 09:37:19 +02005# SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARDc8aa7df2008-10-31 12:26:55 +01006#
7
Masahiro Yamada710f1d32013-10-17 17:34:57 +09008obj-y += fpga.o
9obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
10obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
11obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
12obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053013obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
Masahiro Yamada710f1d32013-10-17 17:34:57 +090014obj-$(CONFIG_FPGA_XILINX) += xilinx.o
15obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
Jean-Christophe PLAGNIOL-VILLARDc8aa7df2008-10-31 12:26:55 +010016ifdef CONFIG_FPGA_ALTERA
Masahiro Yamada710f1d32013-10-17 17:34:57 +090017obj-y += altera.o
18obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
19obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
20obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
Stefan Roeseff9c4c52016-02-12 13:48:02 +010021obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
Pavel Machek230fe9b2014-09-08 14:08:45 +020022obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
Tien Fong Chee6867e192017-07-26 13:05:38 +080023obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
Tien Fong Chee2baa9972017-07-26 13:05:43 +080024obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
Jean-Christophe PLAGNIOL-VILLARDc8aa7df2008-10-31 12:26:55 +010025endif