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wdenk38635852002-08-27 05:55:31 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
d4f5c722005-08-12 21:16:13 +020025/*
26 * Support for read and write access to EEPROM like memory devices. This
27 * includes regular EEPROM as well as FRAM (ferroelectic nonvolaile RAM).
28 * FRAM devices read and write data at bus speed. In particular, there is no
29 * write delay. Also, there is no limit imposed on the numer of bytes that can
30 * be transferred with a single read or write.
Wolfgang Denk6617aae2005-08-19 00:46:54 +020031 *
d4f5c722005-08-12 21:16:13 +020032 * Use the following configuration options to ensure no unneeded performance
33 * degradation (typical for EEPROM) is incured for FRAM memory:
Wolfgang Denk6617aae2005-08-19 00:46:54 +020034 *
d4f5c722005-08-12 21:16:13 +020035 * #define CFG_I2C_FRAM
36 * #undef CFG_EEPROM_PAGE_WRITE_DELAY_MS
37 *
38 */
39
wdenk38635852002-08-27 05:55:31 +000040#include <common.h>
41#include <config.h>
42#include <command.h>
43#include <i2c.h>
44
45#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) || defined(CFG_ENV_IS_IN_EEPROM)
46
47extern void eeprom_init (void);
48extern int eeprom_read (unsigned dev_addr, unsigned offset,
49 uchar *buffer, unsigned cnt);
50extern int eeprom_write (unsigned dev_addr, unsigned offset,
51 uchar *buffer, unsigned cnt);
52#endif
53
54
55#if defined(CFG_EEPROM_X40430)
56 /* Maximum number of times to poll for acknowledge after write */
57#define MAX_ACKNOWLEDGE_POLLS 10
58#endif
59
60/* ------------------------------------------------------------------------- */
61
62#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
63int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
64{
65 const char *const fmt =
66 "\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
67
68#if defined(CFG_I2C_MULTI_EEPROMS)
69 if (argc == 6) {
70 ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
71 ulong addr = simple_strtoul (argv[3], NULL, 16);
72 ulong off = simple_strtoul (argv[4], NULL, 16);
73 ulong cnt = simple_strtoul (argv[5], NULL, 16);
74#else
75 if (argc == 5) {
76 ulong dev_addr = CFG_DEF_EEPROM_ADDR;
77 ulong addr = simple_strtoul (argv[2], NULL, 16);
78 ulong off = simple_strtoul (argv[3], NULL, 16);
79 ulong cnt = simple_strtoul (argv[4], NULL, 16);
80#endif /* CFG_I2C_MULTI_EEPROMS */
81
82# ifndef CONFIG_SPI
83 eeprom_init ();
84# endif /* !CONFIG_SPI */
85
86 if (strcmp (argv[1], "read") == 0) {
87 int rcode;
88
89 printf (fmt, dev_addr, argv[1], addr, off, cnt);
90
91 rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);
92
wdenk4b9206e2004-03-23 22:14:11 +000093 puts ("done\n");
wdenk38635852002-08-27 05:55:31 +000094 return rcode;
95 } else if (strcmp (argv[1], "write") == 0) {
96 int rcode;
97
98 printf (fmt, dev_addr, argv[1], addr, off, cnt);
99
100 rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
101
wdenk4b9206e2004-03-23 22:14:11 +0000102 puts ("done\n");
wdenk38635852002-08-27 05:55:31 +0000103 return rcode;
104 }
105 }
106
107 printf ("Usage:\n%s\n", cmdtp->usage);
108 return 1;
109}
110#endif /* CFG_CMD_EEPROM */
111
112/*-----------------------------------------------------------------------
113 *
114 * for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
115 * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
116 *
117 * for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
118 * 0x00000nxx for EEPROM address selectors and page number at n.
119 */
120
121#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) || defined(CFG_ENV_IS_IN_EEPROM)
122
123#ifndef CONFIG_SPI
124#if !defined(CFG_I2C_EEPROM_ADDR_LEN) || CFG_I2C_EEPROM_ADDR_LEN < 1 || CFG_I2C_EEPROM_ADDR_LEN > 2
125#error CFG_I2C_EEPROM_ADDR_LEN must be 1 or 2
126#endif
127#endif
128
129int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
130{
131 unsigned end = offset + cnt;
132 unsigned blk_off;
133 int rcode = 0;
134
135 /* Read data until done or would cross a page boundary.
136 * We must write the address again when changing pages
137 * because the next page may be in a different device.
138 */
139 while (offset < end) {
d4f5c722005-08-12 21:16:13 +0200140 unsigned alen, len;
141#if !defined(CFG_I2C_FRAM)
142 unsigned maxlen;
143#endif
144
wdenk38635852002-08-27 05:55:31 +0000145#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
146 uchar addr[2];
147
148 blk_off = offset & 0xFF; /* block offset */
149
150 addr[0] = offset >> 8; /* block number */
151 addr[1] = blk_off; /* block offset */
152 alen = 2;
153#else
154 uchar addr[3];
155
156 blk_off = offset & 0xFF; /* block offset */
157
158 addr[0] = offset >> 16; /* block number */
159 addr[1] = offset >> 8; /* upper address octet */
160 addr[2] = blk_off; /* lower address octet */
161 alen = 3;
162#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
163
164 addr[0] |= dev_addr; /* insert device address */
165
d4f5c722005-08-12 21:16:13 +0200166 len = end - offset;
167
168 /*
169 * For a FRAM device there is no limit on the number of the
170 * bytes that can be ccessed with the single read or write
171 * operation.
172 */
173#if !defined(CFG_I2C_FRAM)
wdenk38635852002-08-27 05:55:31 +0000174 maxlen = 0x100 - blk_off;
175 if (maxlen > I2C_RXTX_LEN)
176 maxlen = I2C_RXTX_LEN;
wdenk38635852002-08-27 05:55:31 +0000177 if (len > maxlen)
178 len = maxlen;
d4f5c722005-08-12 21:16:13 +0200179#endif
180
wdenk38635852002-08-27 05:55:31 +0000181#ifdef CONFIG_SPI
182 spi_read (addr, alen, buffer, len);
183#else
184 if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
185 rcode = 1;
186#endif
187 buffer += len;
188 offset += len;
189 }
d4f5c722005-08-12 21:16:13 +0200190
wdenk38635852002-08-27 05:55:31 +0000191 return rcode;
192}
193
194/*-----------------------------------------------------------------------
195 *
196 * for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
197 * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
198 *
199 * for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
200 * 0x00000nxx for EEPROM address selectors and page number at n.
201 */
202
203int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
204{
205 unsigned end = offset + cnt;
206 unsigned blk_off;
207 int rcode = 0;
208
209#if defined(CFG_EEPROM_X40430)
210 uchar contr_r_addr[2];
211 uchar addr_void[2];
212 uchar contr_reg[2];
213 uchar ctrl_reg_v;
214 int i;
215#endif
216
217 /* Write data until done or would cross a write page boundary.
218 * We must write the address again when changing pages
219 * because the address counter only increments within a page.
220 */
221
222 while (offset < end) {
d4f5c722005-08-12 21:16:13 +0200223 unsigned alen, len;
224#if !defined(CFG_I2C_FRAM)
225 unsigned maxlen;
226#endif
227
wdenk38635852002-08-27 05:55:31 +0000228#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
229 uchar addr[2];
230
231 blk_off = offset & 0xFF; /* block offset */
232
233 addr[0] = offset >> 8; /* block number */
234 addr[1] = blk_off; /* block offset */
235 alen = 2;
236#else
237 uchar addr[3];
238
239 blk_off = offset & 0xFF; /* block offset */
240
241 addr[0] = offset >> 16; /* block number */
242 addr[1] = offset >> 8; /* upper address octet */
243 addr[2] = blk_off; /* lower address octet */
244 alen = 3;
245#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
246
247 addr[0] |= dev_addr; /* insert device address */
248
d4f5c722005-08-12 21:16:13 +0200249 len = end - offset;
250
251 /*
252 * For a FRAM device there is no limit on the number of the
253 * bytes that can be ccessed with the single read or write
254 * operation.
255 */
256#if !defined(CFG_I2C_FRAM)
257
wdenk38635852002-08-27 05:55:31 +0000258#if defined(CFG_EEPROM_PAGE_WRITE_BITS)
259
260#define EEPROM_PAGE_SIZE (1 << CFG_EEPROM_PAGE_WRITE_BITS)
261#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
262
263 maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
264#else
265 maxlen = 0x100 - blk_off;
266#endif
267 if (maxlen > I2C_RXTX_LEN)
268 maxlen = I2C_RXTX_LEN;
269
wdenk38635852002-08-27 05:55:31 +0000270 if (len > maxlen)
271 len = maxlen;
d4f5c722005-08-12 21:16:13 +0200272#endif
273
wdenk38635852002-08-27 05:55:31 +0000274#ifdef CONFIG_SPI
275 spi_write (addr, alen, buffer, len);
276#else
277#if defined(CFG_EEPROM_X40430)
278 /* Get the value of the control register.
279 * Set current address (internal pointer in the x40430)
280 * to 0x1ff.
281 */
282 contr_r_addr[0] = 9;
283 contr_r_addr[1] = 0xff;
284 addr_void[0] = 0;
285 addr_void[1] = addr[1];
286#ifdef CFG_I2C_EEPROM_ADDR
287 contr_r_addr[0] |= CFG_I2C_EEPROM_ADDR;
288 addr_void[0] |= CFG_I2C_EEPROM_ADDR;
289#endif
290 contr_reg[0] = 0xff;
291 if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
292 rcode = 1;
293 }
294 ctrl_reg_v = contr_reg[0];
295
296 /* Are any of the eeprom blocks write protected?
297 */
298 if (ctrl_reg_v & 0x18) {
299 ctrl_reg_v &= ~0x18; /* reset block protect bits */
300 ctrl_reg_v |= 0x02; /* set write enable latch */
301 ctrl_reg_v &= ~0x04; /* clear RWEL */
302
303 /* Set write enable latch.
304 */
305 contr_reg[0] = 0x02;
306 if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
307 rcode = 1;
308 }
309
310 /* Set register write enable latch.
311 */
312 contr_reg[0] = 0x06;
313 if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
314 rcode = 1;
315 }
316
317 /* Modify ctrl register.
318 */
319 contr_reg[0] = ctrl_reg_v;
320 if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
321 rcode = 1;
322 }
323
324 /* The write (above) is an operation on NV memory.
325 * These can take some time (~5ms), and the device
326 * will not respond to further I2C messages till
327 * it's completed the write.
328 * So poll device for an I2C acknowledge.
329 * When we get one we know we can continue with other
330 * operations.
331 */
332 contr_reg[0] = 0;
333 for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
wdenkaacf9a42003-01-17 16:27:01 +0000334 if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
wdenk38635852002-08-27 05:55:31 +0000335 break; /* got ack */
336#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
337 udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
338#endif
339 }
340 if (i == MAX_ACKNOWLEDGE_POLLS) {
wdenk4b9206e2004-03-23 22:14:11 +0000341 puts ("EEPROM poll acknowledge failed\n");
wdenk38635852002-08-27 05:55:31 +0000342 rcode = 1;
343 }
344 }
345
346 /* Is the write enable latch on?.
347 */
348 else if (!(ctrl_reg_v & 0x02)) {
349 /* Set write enable latch.
350 */
351 contr_reg[0] = 0x02;
352 if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
353 rcode = 1;
354 }
355 }
356 /* Write is enabled ... now write eeprom value.
357 */
358#endif
359 if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
360 rcode = 1;
361
362#endif
363 buffer += len;
364 offset += len;
365
366#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
367 udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
368#endif
369 }
370 return rcode;
371}
372
wdenk6dd652f2003-06-19 23:40:20 +0000373#ifndef CONFIG_SPI
374int
375eeprom_probe (unsigned dev_addr, unsigned offset)
376{
377 unsigned char chip;
378
379 /* Probe the chip address
380 */
381#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
382 chip = offset >> 8; /* block number */
383#else
384 chip = offset >> 16; /* block number */
385#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
386
387 chip |= dev_addr; /* insert device address */
388
389 return (i2c_probe (chip));
390}
391#endif
392
wdenk38635852002-08-27 05:55:31 +0000393/*-----------------------------------------------------------------------
394 * Set default values
395 */
396#ifndef CFG_I2C_SPEED
397#define CFG_I2C_SPEED 50000
398#endif
399
400#ifndef CFG_I2C_SLAVE
401#define CFG_I2C_SLAVE 0xFE
402#endif
403
404void eeprom_init (void)
405{
406#if defined(CONFIG_SPI)
407 spi_init_f ();
408#endif
409#if defined(CONFIG_HARD_I2C) || \
410 defined(CONFIG_SOFT_I2C)
411 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
412#endif
413}
414/*-----------------------------------------------------------------------
415 */
416#endif /* CFG_CMD_EEPROM */
wdenk8bde7f72003-06-27 21:31:46 +0000417/***************************************************/
418
419#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
420
421#ifdef CFG_I2C_MULTI_EEPROMS
wdenk0d498392003-07-01 21:06:45 +0000422U_BOOT_CMD(
423 eeprom, 6, 1, do_eeprom,
wdenk8bde7f72003-06-27 21:31:46 +0000424 "eeprom - EEPROM sub-system\n",
425 "read devaddr addr off cnt\n"
426 "eeprom write devaddr addr off cnt\n"
427 " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'\n"
428);
429#else /* One EEPROM */
wdenk0d498392003-07-01 21:06:45 +0000430U_BOOT_CMD(
431 eeprom, 5, 1, do_eeprom,
wdenk8bde7f72003-06-27 21:31:46 +0000432 "eeprom - EEPROM sub-system\n",
433 "read addr off cnt\n"
434 "eeprom write addr off cnt\n"
435 " - read/write `cnt' bytes at EEPROM offset `off'\n"
436);
437#endif /* CFG_I2C_MULTI_EEPROMS */
438
439#endif /* CFG_CMD_EEPROM */