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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chin Liang Seed8c67dc2014-06-10 01:10:21 -05002/*
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
Chin Liang Seed8c67dc2014-06-10 01:10:21 -05004 */
5
Marek Vasutcf89ef82019-10-03 14:47:07 +02006#include <clk.h>
Chin Liang Seed8c67dc2014-06-10 01:10:21 -05007#include <common.h>
Marek Vasutcf8c8362019-06-27 01:19:23 +02008#include <dm.h>
Marek Vasutcf89ef82019-10-03 14:47:07 +02009#include <reset.h>
Marek Vasutcf8c8362019-06-27 01:19:23 +020010#include <wdt.h>
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050011#include <asm/io.h>
12#include <asm/utils.h>
Simon Glasscd93d622020-05-10 11:40:13 -060013#include <linux/bitops.h>
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050014
15#define DW_WDT_CR 0x00
16#define DW_WDT_TORR 0x04
17#define DW_WDT_CRR 0x0C
18
19#define DW_WDT_CR_EN_OFFSET 0x00
20#define DW_WDT_CR_RMOD_OFFSET 0x01
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050021#define DW_WDT_CRR_RESTART_VAL 0x76
22
Marek Vasutcf8c8362019-06-27 01:19:23 +020023struct designware_wdt_priv {
24 void __iomem *base;
Marek Vasutcf89ef82019-10-03 14:47:07 +020025 unsigned int clk_khz;
Marek Vasutcf8c8362019-06-27 01:19:23 +020026};
27
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050028/*
29 * Set the watchdog time interval.
30 * Counter is 32 bit.
31 */
Marek Vasutcf8c8362019-06-27 01:19:23 +020032static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
33 unsigned int timeout)
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050034{
35 signed int i;
36
37 /* calculate the timeout range value */
Marek Vasutcf8c8362019-06-27 01:19:23 +020038 i = log_2_n_round_up(timeout * clk_khz) - 16;
39 i = clamp(i, 0, 15);
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050040
Marek Vasutcf8c8362019-06-27 01:19:23 +020041 writel(i | (i << 4), base + DW_WDT_TORR);
42
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050043 return 0;
44}
45
Marek Vasutcf8c8362019-06-27 01:19:23 +020046static void designware_wdt_enable(void __iomem *base)
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050047{
Marek Vasutcf89ef82019-10-03 14:47:07 +020048 writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR);
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050049}
50
Marek Vasutcf8c8362019-06-27 01:19:23 +020051static unsigned int designware_wdt_is_enabled(void __iomem *base)
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050052{
Marek Vasutcf8c8362019-06-27 01:19:23 +020053 return readl(base + DW_WDT_CR) & BIT(0);
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050054}
55
Marek Vasutcf8c8362019-06-27 01:19:23 +020056static void designware_wdt_reset_common(void __iomem *base)
57{
58 if (designware_wdt_is_enabled(base))
59 /* restart the watchdog counter */
60 writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
61}
62
63#if !CONFIG_IS_ENABLED(WDT)
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050064void hw_watchdog_reset(void)
65{
Marek Vasutcf8c8362019-06-27 01:19:23 +020066 designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050067}
68
69void hw_watchdog_init(void)
70{
71 /* reset to disable the watchdog */
72 hw_watchdog_reset();
73 /* set timer in miliseconds */
Marek Vasutcf8c8362019-06-27 01:19:23 +020074 designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
75 CONFIG_DW_WDT_CLOCK_KHZ,
76 CONFIG_WATCHDOG_TIMEOUT_MSECS);
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050077 /* enable the watchdog */
Marek Vasutcf8c8362019-06-27 01:19:23 +020078 designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
Chin Liang Seed8c67dc2014-06-10 01:10:21 -050079 /* reset the watchdog */
80 hw_watchdog_reset();
81}
Marek Vasutcf8c8362019-06-27 01:19:23 +020082#else
83static int designware_wdt_reset(struct udevice *dev)
84{
85 struct designware_wdt_priv *priv = dev_get_priv(dev);
86
87 designware_wdt_reset_common(priv->base);
88
89 return 0;
90}
91
92static int designware_wdt_stop(struct udevice *dev)
93{
94 struct designware_wdt_priv *priv = dev_get_priv(dev);
95
96 designware_wdt_reset(dev);
Marek Vasutcf89ef82019-10-03 14:47:07 +020097 writel(0, priv->base + DW_WDT_CR);
Marek Vasutcf8c8362019-06-27 01:19:23 +020098
99 return 0;
100}
101
102static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
103{
104 struct designware_wdt_priv *priv = dev_get_priv(dev);
105
106 designware_wdt_stop(dev);
107
108 /* set timer in miliseconds */
Marek Vasutcf89ef82019-10-03 14:47:07 +0200109 designware_wdt_settimeout(priv->base, priv->clk_khz, timeout);
Marek Vasutcf8c8362019-06-27 01:19:23 +0200110
111 designware_wdt_enable(priv->base);
112
113 /* reset the watchdog */
114 return designware_wdt_reset(dev);
115}
116
117static int designware_wdt_probe(struct udevice *dev)
118{
119 struct designware_wdt_priv *priv = dev_get_priv(dev);
Marek Vasutcf89ef82019-10-03 14:47:07 +0200120 __maybe_unused int ret;
Marek Vasutcf8c8362019-06-27 01:19:23 +0200121
122 priv->base = dev_remap_addr(dev);
123 if (!priv->base)
124 return -EINVAL;
125
Marek Vasutcf89ef82019-10-03 14:47:07 +0200126#if CONFIG_IS_ENABLED(CLK)
127 struct clk clk;
128
129 ret = clk_get_by_index(dev, 0, &clk);
130 if (ret)
131 return ret;
132
Jack Mitchelld9b9c912020-09-17 10:30:40 +0100133 priv->clk_khz = clk_get_rate(&clk) / 1000;
Marek Vasutcf89ef82019-10-03 14:47:07 +0200134 if (!priv->clk_khz)
135 return -EINVAL;
136#else
137 priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ;
138#endif
139
140#if CONFIG_IS_ENABLED(DM_RESET)
141 struct reset_ctl_bulk resets;
142
143 ret = reset_get_bulk(dev, &resets);
144 if (ret)
145 return ret;
146
147 ret = reset_deassert_bulk(&resets);
148 if (ret)
149 return ret;
150#endif
151
Marek Vasutcf8c8362019-06-27 01:19:23 +0200152 /* reset to disable the watchdog */
153 return designware_wdt_stop(dev);
154}
155
156static const struct wdt_ops designware_wdt_ops = {
157 .start = designware_wdt_start,
158 .reset = designware_wdt_reset,
159 .stop = designware_wdt_stop,
160};
161
162static const struct udevice_id designware_wdt_ids[] = {
163 { .compatible = "snps,dw-wdt"},
164 {}
165};
166
167U_BOOT_DRIVER(designware_wdt) = {
168 .name = "designware_wdt",
169 .id = UCLASS_WDT,
170 .of_match = designware_wdt_ids,
Simon Glass41575d82020-12-03 16:55:17 -0700171 .priv_auto = sizeof(struct designware_wdt_priv),
Marek Vasutcf8c8362019-06-27 01:19:23 +0200172 .probe = designware_wdt_probe,
173 .ops = &designware_wdt_ops,
174 .flags = DM_FLAG_PRE_RELOC,
175};
Chin Liang Seed8c67dc2014-06-10 01:10:21 -0500176#endif