| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| maxims@google.com | c93adc0 | 2017-04-17 12:00:25 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2017 Google, Inc |
| Chia-Wei, Wang | 611a28c | 2020-10-15 10:25:13 +0800 | [diff] [blame] | 4 | * Copyright 2020 ASPEED Technology Inc. |
| maxims@google.com | c93adc0 | 2017-04-17 12:00:25 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_ |
| 8 | #define _ABI_MACH_ASPEED_AST2500_RESET_H_ |
| 9 | |
| Chia-Wei, Wang | 611a28c | 2020-10-15 10:25:13 +0800 | [diff] [blame] | 10 | #define ASPEED_RESET_CRT1 (37) |
| 11 | #define ASPEED_RESET_RESERVED36 (36) |
| 12 | #define ASPEED_RESET_RESERVED35 (35) |
| 13 | #define ASPEED_RESET_RESERVED34 (34) |
| 14 | #define ASPEED_RESET_RESERVED33 (33) |
| 15 | #define ASPEED_RESET_RESERVED32 (32) |
| 16 | #define ASPEED_RESET_RESERVED31 (31) |
| 17 | #define ASPEED_RESET_RESERVED30 (30) |
| 18 | #define ASPEED_RESET_RESERVED29 (29) |
| 19 | #define ASPEED_RESET_RESERVED28 (28) |
| 20 | #define ASPEED_RESET_RESERVED27 (27) |
| 21 | #define ASPEED_RESET_RESERVED26 (26) |
| 22 | #define ASPEED_RESET_XDMA (25) |
| 23 | #define ASPEED_RESET_MCTP (24) |
| 24 | #define ASPEED_RESET_ADC (23) |
| 25 | #define ASPEED_RESET_JTAG_MASTER (22) |
| 26 | #define ASPEED_RESET_RESERVED21 (21) |
| 27 | #define ASPEED_RESET_RESERVED20 (20) |
| 28 | #define ASPEED_RESET_RESERVED19 (19) |
| 29 | #define ASPEED_RESET_MIC (18) |
| 30 | #define ASPEED_RESET_RESERVED17 (17) |
| 31 | #define ASPEED_RESET_SDIO (16) |
| 32 | #define ASPEED_RESET_UHCI (15) |
| 33 | #define ASPEED_RESET_EHCI_P1 (14) |
| 34 | #define ASPEED_RESET_CRT (13) |
| 35 | #define ASPEED_RESET_MAC2 (12) |
| 36 | #define ASPEED_RESET_MAC1 (11) |
| 37 | #define ASPEED_RESET_PECI (10) |
| 38 | #define ASPEED_RESET_PWM (9) |
| 39 | #define ASPEED_RESET_PCI_VGA (8) |
| 40 | #define ASPEED_RESET_2D (7) |
| 41 | #define ASPEED_RESET_VIDEO (6) |
| 42 | #define ASPEED_RESET_LPC_ESPI (5) |
| 43 | #define ASPEED_RESET_HACE (4) |
| 44 | #define ASPEED_RESET_EHCI_P2 (3) |
| 45 | #define ASPEED_RESET_I2C (2) |
| 46 | #define ASPEED_RESET_AHB (1) |
| 47 | #define ASPEED_RESET_SDRAM (0) |
| maxims@google.com | c93adc0 | 2017-04-17 12:00:25 -0700 | [diff] [blame] | 48 | |
| 49 | #endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */ |