| Simon Glass | e2d934b | 2023-07-15 21:39:18 -0600 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Modified from coreboot bochs.c |
| 4 | */ |
| 5 | |
| 6 | #define LOG_CATEGORY UCLASS_VIDEO |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <dm.h> |
| 10 | #include <log.h> |
| 11 | #include <pci.h> |
| 12 | #include <video.h> |
| 13 | #include <asm/io.h> |
| 14 | #include <asm/mtrr.h> |
| 15 | #include <linux/sizes.h> |
| 16 | #include "bochs.h" |
| 17 | |
| 18 | static int xsize = CONFIG_VIDEO_BOCHS_SIZE_X; |
| 19 | static int ysize = CONFIG_VIDEO_BOCHS_SIZE_Y; |
| 20 | |
| 21 | static void bochs_write(void *mmio, int index, int val) |
| 22 | { |
| 23 | writew(val, mmio + MMIO_BASE + index * 2); |
| 24 | } |
| 25 | |
| 26 | static int bochs_read(void *mmio, int index) |
| 27 | { |
| 28 | return readw(mmio + MMIO_BASE + index * 2); |
| 29 | } |
| 30 | |
| 31 | static void bochs_vga_write(int index, uint8_t val) |
| 32 | { |
| 33 | outb(val, VGA_INDEX); |
| 34 | } |
| 35 | |
| 36 | static int bochs_init_fb(struct udevice *dev) |
| 37 | { |
| 38 | struct video_uc_plat *plat = dev_get_uclass_plat(dev); |
| 39 | struct video_priv *uc_priv = dev_get_uclass_priv(dev); |
| 40 | ulong fb; |
| 41 | void *mmio; |
| 42 | int id, mem; |
| 43 | |
| 44 | log_debug("probing %s at PCI %x\n", dev->name, dm_pci_get_bdf(dev)); |
| 45 | fb = dm_pci_read_bar32(dev, 0); |
| 46 | if (!fb) |
| 47 | return log_msg_ret("fb", -EIO); |
| 48 | |
| 49 | /* MMIO bar supported since qemu 3.0+ */ |
| 50 | mmio = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_TYPE, |
| 51 | PCI_REGION_MEM); |
| 52 | |
| 53 | if (!mmio) |
| 54 | return log_msg_ret("map", -EIO); |
| 55 | |
| 56 | /* bochs dispi detection */ |
| 57 | id = bochs_read(mmio, INDEX_ID); |
| 58 | if ((id & 0xfff0) != ID0) { |
| 59 | log_debug("ID mismatch\n"); |
| 60 | return -EPROTONOSUPPORT; |
| 61 | } |
| 62 | mem = bochs_read(mmio, INDEX_VIDEO_MEMORY_64K) * SZ_64K; |
| 63 | log_debug("QEMU VGA: bochs @ %p: %d MiB FB at %lx\n", mmio, mem / SZ_1M, |
| 64 | fb); |
| 65 | |
| 66 | uc_priv->xsize = xsize; |
| 67 | uc_priv->ysize = ysize; |
| 68 | uc_priv->bpix = VIDEO_BPP32; |
| 69 | |
| 70 | /* setup video mode */ |
| 71 | bochs_write(mmio, INDEX_ENABLE, 0); |
| 72 | bochs_write(mmio, INDEX_BANK, 0); |
| 73 | bochs_write(mmio, INDEX_BPP, VNBITS(uc_priv->bpix)); |
| 74 | bochs_write(mmio, INDEX_XRES, xsize); |
| 75 | bochs_write(mmio, INDEX_YRES, ysize); |
| 76 | bochs_write(mmio, INDEX_VIRT_WIDTH, xsize); |
| 77 | bochs_write(mmio, INDEX_VIRT_HEIGHT, ysize); |
| 78 | bochs_write(mmio, INDEX_X_OFFSET, 0); |
| 79 | bochs_write(mmio, INDEX_Y_OFFSET, 0); |
| 80 | bochs_write(mmio, INDEX_ENABLE, ENABLED | LFB_ENABLED); |
| 81 | |
| 82 | bochs_vga_write(0, 0x20); /* disable blanking */ |
| 83 | |
| 84 | plat->base = fb; |
| 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | static int bochs_video_probe(struct udevice *dev) |
| 90 | { |
| 91 | int ret; |
| 92 | |
| 93 | ret = bochs_init_fb(dev); |
| 94 | if (ret) |
| 95 | return log_ret(ret); |
| 96 | |
| 97 | return 0; |
| 98 | } |
| 99 | |
| 100 | static int bochs_video_bind(struct udevice *dev) |
| 101 | { |
| 102 | struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); |
| 103 | |
| 104 | /* Set the maximum supported resolution */ |
| 105 | uc_plat->size = 2560 * 1600 * 4; |
| 106 | log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); |
| 107 | |
| 108 | return 0; |
| 109 | } |
| 110 | |
| 111 | U_BOOT_DRIVER(bochs_video) = { |
| 112 | .name = "bochs_video", |
| 113 | .id = UCLASS_VIDEO, |
| 114 | .bind = bochs_video_bind, |
| 115 | .probe = bochs_video_probe, |
| 116 | }; |
| 117 | |
| 118 | static struct pci_device_id bochs_video_supported[] = { |
| 119 | { PCI_DEVICE(0x1234, 0x1111) }, |
| 120 | { }, |
| 121 | }; |
| 122 | |
| 123 | U_BOOT_PCI_DEVICE(bochs_video, bochs_video_supported); |