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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 476af299b04ef07117bbc3cdef07885e1089967e / . / drivers / serial / serial_sh.h
blob: 4e16e4803c135b05d79097147df7b4f7a717738d [file] [log] [blame]
Nobuhiro Iwamatsu3f6c8e32010-10-26 03:55:15 +0900[diff] [blame]1/*
2 * Copy and modify from linux/drivers/serial/sh-sci.h
3 */
4
5struct uart_port {
6 unsigned long iobase; /* in/out[bwl] */
7 unsigned char *membase; /* read/write[bwl] */
8 unsigned long mapbase; /* for ioremap */
9 unsigned int type; /* port type */
10};
11
12#define PORT_SCI 52
13#define PORT_SCIF 53
14#define PORT_SCIFA 83
15#define PORT_SCIFB 93
16
17#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
18#include <asm/regs306x.h>
19#endif
20#if defined(CONFIG_H8S2678)
21#include <asm/regs267x.h>
22#endif
23
24#if defined(CONFIG_CPU_SH7706) || \
25 defined(CONFIG_CPU_SH7707) || \
26 defined(CONFIG_CPU_SH7708) || \
27 defined(CONFIG_CPU_SH7709)
28# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
29# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
30# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
31#elif defined(CONFIG_CPU_SH7705)
32# define SCIF0 0xA4400000
33# define SCIF2 0xA4410000
34# define SCSMR_Ir 0xA44A0000
35# define IRDA_SCIF SCIF0
36# define SCPCR 0xA4000116
37# define SCPDR 0xA4000136
38
39/* Set the clock source,
40 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
41 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
42 */
43# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
44#elif defined(CONFIG_CPU_SH7720) || \
45 defined(CONFIG_CPU_SH7721) || \
46 defined(CONFIG_ARCH_SH7367) || \
47 defined(CONFIG_ARCH_SH7377) || \
48 defined(CONFIG_ARCH_SH7372)
49# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
50# define PORT_PTCR 0xA405011EUL
51# define PORT_PVCR 0xA4050122UL
52# define SCIF_ORER 0x0200 /* overrun error bit */
53#elif defined(CONFIG_SH_RTS7751R2D)
54# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
55# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
56# define SCIF_ORER 0x0001 /* overrun error bit */
57# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
58#elif defined(CONFIG_CPU_SH7750) || \
59 defined(CONFIG_CPU_SH7750R) || \
60 defined(CONFIG_CPU_SH7750S) || \
61 defined(CONFIG_CPU_SH7091) || \
62 defined(CONFIG_CPU_SH7751) || \
63 defined(CONFIG_CPU_SH7751R)
64# define SCSPTR1 0xffe0001c /* 8 bit SCI */
65# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
66# define SCIF_ORER 0x0001 /* overrun error bit */
67# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
70#elif defined(CONFIG_CPU_SH7760)
71# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
72# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
73# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
74# define SCIF_ORER 0x0001 /* overrun error bit */
75# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
76#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
77# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
78# define SCIF_ORER 0x0001 /* overrun error bit */
79# define PACR 0xa4050100
80# define PBCR 0xa4050102
81# define SCSCR_INIT(port) 0x3B
82#elif defined(CONFIG_CPU_SH7343)
83# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
84# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
85# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
86# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
87# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
88#elif defined(CONFIG_CPU_SH7722)
89# define PADR 0xA4050120
Nobuhiro Iwamatsu99057062010-11-24 13:24:33 +0900[diff] [blame]90# undef PSDR
Nobuhiro Iwamatsu3f6c8e32010-10-26 03:55:15 +0900[diff] [blame]91# define PSDR 0xA405013e
92# define PWDR 0xA4050166
93# define PSCR 0xA405011E
94# define SCIF_ORER 0x0001 /* overrun error bit */
95# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
96#elif defined(CONFIG_CPU_SH7366)
97# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
98# define SCSPTR0 SCPDR0
99# define SCIF_ORER 0x0001 /* overrun error bit */
100# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
101#elif defined(CONFIG_CPU_SH7723)
102# define SCSPTR0 0xa4050160
103# define SCSPTR1 0xa405013e
104# define SCSPTR2 0xa4050160
105# define SCSPTR3 0xa405013e
106# define SCSPTR4 0xa4050128
107# define SCSPTR5 0xa4050128
108# define SCIF_ORER 0x0001 /* overrun error bit */
109# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
110#elif defined(CONFIG_CPU_SH7724)
111# define SCIF_ORER 0x0001 /* overrun error bit */
112# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
113 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
114 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
115#elif defined(CONFIG_CPU_SH4_202)
116# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
117# define SCIF_ORER 0x0001 /* overrun error bit */
118# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
119#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
120# define SCIF_BASE_ADDR 0x01030000
121# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
122# define SCIF_PTR2_OFFS 0x0000020
123# define SCIF_LSR2_OFFS 0x0000024
124# define SCSPTR\
125 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
126# define SCLSR2\
127 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
128# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
129#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
130# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
131# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
132#elif defined(CONFIG_H8S2678)
133# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
134# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
135#elif defined(CONFIG_CPU_SH7757)
136# define SCSPTR0 0xfe4b0020
137# define SCSPTR1 0xfe4b0020
138# define SCSPTR2 0xfe4b0020
139# define SCIF_ORER 0x0001
140# define SCSCR_INIT(port) 0x38
141# define SCIF_ONLY
142#elif defined(CONFIG_CPU_SH7763)
143# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
144# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
145# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
146# define SCIF_ORER 0x0001 /* overrun error bit */
147# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
148#elif defined(CONFIG_CPU_SH7770)
149# define SCSPTR0 0xff923020 /* 16 bit SCIF */
150# define SCSPTR1 0xff924020 /* 16 bit SCIF */
151# define SCSPTR2 0xff925020 /* 16 bit SCIF */
152# define SCIF_ORER 0x0001 /* overrun error bit */
153# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
154#elif defined(CONFIG_CPU_SH7780)
155# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
156# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
157# define SCIF_ORER 0x0001 /* Overrun error bit */
158
159#if defined(CONFIG_SH_SH2007)
160/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
161# define SCSCR_INIT(port) 0x38
162#else
163/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
164# define SCSCR_INIT(port) 0x3a
165#endif
166
167#elif defined(CONFIG_CPU_SH7785) || \
168 defined(CONFIG_CPU_SH7786)
169# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
170# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
171# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
172# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
173# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
174# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
175# define SCIF_ORER 0x0001 /* Overrun error bit */
176# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
177#elif defined(CONFIG_CPU_SH7201) || \
178 defined(CONFIG_CPU_SH7203) || \
179 defined(CONFIG_CPU_SH7206) || \
Phil Edworthy7fbeb642011-06-01 07:35:13 +0100[diff] [blame]180 defined(CONFIG_CPU_SH7263) || \
181 defined(CONFIG_CPU_SH7264)
Nobuhiro Iwamatsu3f6c8e32010-10-26 03:55:15 +0900[diff] [blame]182# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
183# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
184# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
185# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
186# if defined(CONFIG_CPU_SH7201)
187# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
188# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
189# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
190# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
191# endif
192# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
193#elif defined(CONFIG_CPU_SH7619)
194# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
195# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
196# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
197# define SCIF_ORER 0x0001 /* overrun error bit */
198# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
199#elif defined(CONFIG_CPU_SHX3)
200# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
201# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
202# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
203# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
204# define SCIF_ORER 0x0001 /* Overrun error bit */
205# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
206#else
207# error CPU subtype not defined
208#endif
209
210/* SCSCR */
211#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
212#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
213#define SCI_CTRL_FLAGS_TE 0x20 /* all */
214#define SCI_CTRL_FLAGS_RE 0x10 /* all */
215#if defined(CONFIG_CPU_SH7750) || \
216 defined(CONFIG_CPU_SH7091) || \
217 defined(CONFIG_CPU_SH7750R) || \
218 defined(CONFIG_CPU_SH7722) || \
219 defined(CONFIG_CPU_SH7750S) || \
220 defined(CONFIG_CPU_SH7751) || \
221 defined(CONFIG_CPU_SH7751R) || \
222 defined(CONFIG_CPU_SH7763) || \
223 defined(CONFIG_CPU_SH7780) || \
224 defined(CONFIG_CPU_SH7785) || \
225 defined(CONFIG_CPU_SH7786) || \
226 defined(CONFIG_CPU_SHX3)
227#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
228#elif defined(CONFIG_CPU_SH7724)
229#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
230#else
231#define SCI_CTRL_FLAGS_REIE 0
232#endif
233/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
234/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
235/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
236/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
237
238/* SCxSR SCI */
239#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
240#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
241#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
242#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
243#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
244#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
245/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
246/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
247
248#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
249
250/* SCxSR SCIF */
251#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
252#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
253#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
254#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
255#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
256#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
257#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
258#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
259
260#if defined(CONFIG_CPU_SH7705) || \
261 defined(CONFIG_CPU_SH7720) || \
262 defined(CONFIG_CPU_SH7721) || \
263 defined(CONFIG_ARCH_SH7367) || \
264 defined(CONFIG_ARCH_SH7377) || \
265 defined(CONFIG_ARCH_SH7372)
266# define SCIF_ORER 0x0200
267# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
268# define SCIF_RFDC_MASK 0x007f
269# define SCIF_TXROOM_MAX 64
270#elif defined(CONFIG_CPU_SH7763)
271# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
272# define SCIF_RFDC_MASK 0x007f
273# define SCIF_TXROOM_MAX 64
274/* SH7763 SCIF2 support */
275# define SCIF2_RFDC_MASK 0x001f
276# define SCIF2_TXROOM_MAX 16
277#else
278# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
279# define SCIF_RFDC_MASK 0x001f
280# define SCIF_TXROOM_MAX 16
281#endif
282
283#ifndef SCIF_ORER
284#define SCIF_ORER 0x0000
285#endif
286
287#define SCxSR_TEND(port)\
288 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
289#define SCxSR_ERRORS(port)\
290 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
291#define SCxSR_RDxF(port)\
292 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
293#define SCxSR_TDxE(port)\
294 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
295#define SCxSR_FER(port)\
296 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
297#define SCxSR_PER(port)\
298 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
299#define SCxSR_BRK(port)\
300 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
301#define SCxSR_ORER(port)\
302 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
303
304#if defined(CONFIG_CPU_SH7705) || \
305 defined(CONFIG_CPU_SH7720) || \
306 defined(CONFIG_CPU_SH7721) || \
307 defined(CONFIG_ARCH_SH7367) || \
308 defined(CONFIG_ARCH_SH7377) || \
309 defined(CONFIG_ARCH_SH7372)
310# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
311# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
312# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
313# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
314#else
315# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
316# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
317# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
318# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
319#endif
320
321/* SCFCR */
322#define SCFCR_RFRST 0x0002
323#define SCFCR_TFRST 0x0004
324#define SCFCR_TCRST 0x4000
325#define SCFCR_MCE 0x0008
326
327#define SCI_MAJOR 204
328#define SCI_MINOR_START 8
329
330/* Generic serial flags */
331#define SCI_RX_THROTTLE 0x0000001
332
333#define SCI_MAGIC 0xbabeface
334
335/*
336 * Events are used to schedule things to happen at timer-interrupt
337 * time, instead of at rs interrupt time.
338 */
339#define SCI_EVENT_WRITE_WAKEUP 0
340
341#define SCI_IN(size, offset)\
342 if ((size) == 8) {\
343 return readb(port->membase + (offset));\
344 } else {\
345 return readw(port->membase + (offset));\
346 }
347#define SCI_OUT(size, offset, value)\
348 if ((size) == 8) {\
349 writeb(value, port->membase + (offset));\
350 } else if ((size) == 16) {\
351 writew(value, port->membase + (offset));\
352 }
353
354#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
355 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
356 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
357 SCI_IN(scif_size, scif_offset)\
358 } else { /* PORT_SCI or PORT_SCIFA */\
359 SCI_IN(sci_size, sci_offset);\
360 }\
361 }\
362static inline void sci_##name##_out(struct uart_port *port,\
363 unsigned int value) {\
364 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
365 SCI_OUT(scif_size, scif_offset, value)\
366 } else { /* PORT_SCI or PORT_SCIFA */\
367 SCI_OUT(sci_size, sci_offset, value);\
368 }\
369}
370
371#ifdef CONFIG_H8300
372/* h8300 don't have SCIF */
373#define CPU_SCIF_FNS(name) \
374 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
375 return 0;\
376 }\
377 static inline void sci_##name##_out(struct uart_port *port,\
378 unsigned int value) {\
379 }
380#else
381#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
382 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
383 SCI_IN(scif_size, scif_offset);\
384 }\
385 static inline void sci_##name##_out(struct uart_port *port,\
386 unsigned int value) {\
387 SCI_OUT(scif_size, scif_offset, value);\
388 }
389#endif
390
391#define CPU_SCI_FNS(name, sci_offset, sci_size)\
392 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
393 SCI_IN(sci_size, sci_offset);\
394 }\
395 static inline void sci_##name##_out(struct uart_port *port,\
396 unsigned int value) {\
397 SCI_OUT(sci_size, sci_offset, value);\
398 }
399
400#if defined(CONFIG_SH3) || \
401 defined(CONFIG_ARCH_SH7367) || \
402 defined(CONFIG_ARCH_SH7377) || \
403 defined(CONFIG_ARCH_SH7372)
404#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
405#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
406 sh4_sci_offset, sh4_sci_size, \
407 sh3_scif_offset, sh3_scif_size, \
408 sh4_scif_offset, sh4_scif_size, \
409 h8_sci_offset, h8_sci_size) \
410 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
411 sh4_scif_offset, sh4_scif_size)
412#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
413 sh4_scif_offset, sh4_scif_size) \
414 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
415#elif defined(CONFIG_CPU_SH7705) || \
416 defined(CONFIG_CPU_SH7720) || \
417 defined(CONFIG_CPU_SH7721) || \
418 defined(CONFIG_ARCH_SH7367) || \
419 defined(CONFIG_ARCH_SH7377)
420#define SCIF_FNS(name, scif_offset, scif_size) \
421 CPU_SCIF_FNS(name, scif_offset, scif_size)
422#elif defined(CONFIG_ARCH_SH7372)
423#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
424 sh4_scifb_offset, sh4_scifb_size) \
425 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
426 sh4_scifb_offset, sh4_scifb_size)
427#define SCIF_FNS(name, scif_offset, scif_size) \
428 CPU_SCIF_FNS(name, scif_offset, scif_size)
429#else
430#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
431 sh4_sci_offset, sh4_sci_size, \
432 sh3_scif_offset, sh3_scif_size,\
433 sh4_scif_offset, sh4_scif_size, \
434 h8_sci_offset, h8_sci_size) \
435 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
436 sh3_scif_offset, sh3_scif_size)
437#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
438 sh4_scif_offset, sh4_scif_size) \
439 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
440#endif
441#elif defined(__H8300H__) || defined(__H8300S__)
442#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
443 sh4_sci_offset, sh4_sci_size, \
444 sh3_scif_offset, sh3_scif_size,\
445 sh4_scif_offset, sh4_scif_size, \
446 h8_sci_offset, h8_sci_size) \
447 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
448#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
449 sh4_scif_offset, sh4_scif_size) \
450 CPU_SCIF_FNS(name)
451#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
452 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
453 sh4_scif_offset, sh4_scif_size) \
454 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
455 sh4_scif_offset, sh4_scif_size)
456 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
457 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
458#else
459#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
460 sh4_sci_offset, sh4_sci_size, \
461 sh3_scif_offset, sh3_scif_size,\
462 sh4_scif_offset, sh4_scif_size, \
463 h8_sci_offset, h8_sci_size) \
464 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
465 sh4_scif_offset, sh4_scif_size)
466#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
467 sh4_scif_offset, sh4_scif_size) \
468 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
469#endif
470
471#if defined(CONFIG_CPU_SH7705) || \
472 defined(CONFIG_CPU_SH7720) || \
473 defined(CONFIG_CPU_SH7721) || \
474 defined(CONFIG_ARCH_SH7367) || \
475 defined(CONFIG_ARCH_SH7377)
476
477SCIF_FNS(SCSMR, 0x00, 16)
478SCIF_FNS(SCBRR, 0x04, 8)
479SCIF_FNS(SCSCR, 0x08, 16)
480SCIF_FNS(SCTDSR, 0x0c, 8)
481SCIF_FNS(SCFER, 0x10, 16)
482SCIF_FNS(SCxSR, 0x14, 16)
483SCIF_FNS(SCFCR, 0x18, 16)
484SCIF_FNS(SCFDR, 0x1c, 16)
485SCIF_FNS(SCxTDR, 0x20, 8)
486SCIF_FNS(SCxRDR, 0x24, 8)
487SCIF_FNS(SCLSR, 0x00, 0)
488#elif defined(CONFIG_ARCH_SH7372)
489SCIF_FNS(SCSMR, 0x00, 16)
490SCIF_FNS(SCBRR, 0x04, 8)
491SCIF_FNS(SCSCR, 0x08, 16)
492SCIF_FNS(SCTDSR, 0x0c, 16)
493SCIF_FNS(SCFER, 0x10, 16)
494SCIF_FNS(SCxSR, 0x14, 16)
495SCIF_FNS(SCFCR, 0x18, 16)
496SCIF_FNS(SCFDR, 0x1c, 16)
497SCIF_FNS(SCTFDR, 0x38, 16)
498SCIF_FNS(SCRFDR, 0x3c, 16)
499SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
500SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
501SCIF_FNS(SCLSR, 0x00, 0)
502#elif defined(CONFIG_CPU_SH7723) ||\
503 defined(CONFIG_CPU_SH7724)
504SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
505SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
506SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
507SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
508SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
509SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
510SCIx_FNS(SCSPTR, 0, 0, 0, 0)
511SCIF_FNS(SCTDSR, 0x0c, 8)
512SCIF_FNS(SCFER, 0x10, 16)
513SCIF_FNS(SCFCR, 0x18, 16)
514SCIF_FNS(SCFDR, 0x1c, 16)
515SCIF_FNS(SCLSR, 0x24, 16)
516#else
517/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
518/* name off sz off sz off sz off sz off sz*/
519SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
520SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
521SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
522SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
523SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
524SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
525SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
526#if defined(CONFIG_CPU_SH7760) || \
527 defined(CONFIG_CPU_SH7780) || \
528 defined(CONFIG_CPU_SH7785) || \
529 defined(CONFIG_CPU_SH7786)
530SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
531SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
532SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
533SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
534SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
535#elif defined(CONFIG_CPU_SH7763)
536SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
537SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
538SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
539SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
540SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
541SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
542SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
543#else
544SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
545#if defined(CONFIG_CPU_SH7722)
546SCIF_FNS(SCSPTR, 0, 0, 0, 0)
547#else
548SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
549#endif
550SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
551#endif
552#endif
553#define sci_in(port, reg) sci_##reg##_in(port)
554#define sci_out(port, reg, value) sci_##reg##_out(port, value)
555
556/* H8/300 series SCI pins assignment */
557#if defined(__H8300H__) || defined(__H8300S__)
558static const struct __attribute__((packed)) {
559 int port; /* GPIO port no */
560 unsigned short rx, tx; /* GPIO bit no */
561} h8300_sci_pins[] = {
562#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
563 { /* SCI0 */
564 .port = H8300_GPIO_P9,
565 .rx = H8300_GPIO_B2,
566 .tx = H8300_GPIO_B0,
567 },
568 { /* SCI1 */
569 .port = H8300_GPIO_P9,
570 .rx = H8300_GPIO_B3,
571 .tx = H8300_GPIO_B1,
572 },
573 { /* SCI2 */
574 .port = H8300_GPIO_PB,
575 .rx = H8300_GPIO_B7,
576 .tx = H8300_GPIO_B6,
577 }
578#elif defined(CONFIG_H8S2678)
579 { /* SCI0 */
580 .port = H8300_GPIO_P3,
581 .rx = H8300_GPIO_B2,
582 .tx = H8300_GPIO_B0,
583 },
584 { /* SCI1 */
585 .port = H8300_GPIO_P3,
586 .rx = H8300_GPIO_B3,
587 .tx = H8300_GPIO_B1,
588 },
589 { /* SCI2 */
590 .port = H8300_GPIO_P5,
591 .rx = H8300_GPIO_B1,
592 .tx = H8300_GPIO_B0,
593 }
594#endif
595};
596#endif
597
598#if defined(CONFIG_CPU_SH7706) || \
599 defined(CONFIG_CPU_SH7707) || \
600 defined(CONFIG_CPU_SH7708) || \
601 defined(CONFIG_CPU_SH7709)
602static inline int sci_rxd_in(struct uart_port *port)
603{
604 if (port->mapbase == 0xfffffe80)
605 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
606 return 1;
607}
608#elif defined(CONFIG_CPU_SH7750) || \
609 defined(CONFIG_CPU_SH7751) || \
610 defined(CONFIG_CPU_SH7751R) || \
611 defined(CONFIG_CPU_SH7750R) || \
612 defined(CONFIG_CPU_SH7750S) || \
613 defined(CONFIG_CPU_SH7091)
614static inline int sci_rxd_in(struct uart_port *port)
615{
616 if (port->mapbase == 0xffe00000)
617 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
618 return 1;
619}
620#elif defined(__H8300H__) || defined(__H8300S__)
621static inline int sci_rxd_in(struct uart_port *port)
622{
623 int ch = (port->mapbase - SMR0) >> 3;
624 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
625}
626#else /* default case for non-SCI processors */
627static inline int sci_rxd_in(struct uart_port *port)
628{
629 return 1;
630}
631#endif
632
633/*
634 * Values for the BitRate Register (SCBRR)
635 *
636 * The values are actually divisors for a frequency which can
637 * be internal to the SH3 (14.7456MHz) or derived from an external
638 * clock source. This driver assumes the internal clock is used;
639 * to support using an external clock source, config options or
640 * possibly command-line options would need to be added.
641 *
642 * Also, to support speeds below 2400 (why?) the lower 2 bits of
643 * the SCSMR register would also need to be set to non-zero values.
644 *
645 * -- Greg Banks 27Feb2000
646 *
647 * Answer: The SCBRR register is only eight bits, and the value in
648 * it gets larger with lower baud rates. At around 2400 (depending on
649 * the peripherial module clock) you run out of bits. However the
650 * lower two bits of SCSMR allow the module clock to be divided down,
651 * scaling the value which is needed in SCBRR.
652 *
653 * -- Stuart Menefy - 23 May 2000
654 *
655 * I meant, why would anyone bother with bitrates below 2400.
656 *
657 * -- Greg Banks - 7Jul2000
658 *
659 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
660 * tape reader as a console!
661 *
662 * -- Mitch Davis - 15 Jul 2000
663 */
664
665#if (defined(CONFIG_CPU_SH7780) || \
666 defined(CONFIG_CPU_SH7785) || \
667 defined(CONFIG_CPU_SH7786)) && \
668 !defined(CONFIG_SH_SH2007)
669#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
670#elif defined(CONFIG_CPU_SH7705) || \
671 defined(CONFIG_CPU_SH7720) || \
672 defined(CONFIG_CPU_SH7721) || \
673 defined(CONFIG_ARCH_SH7367) || \
674 defined(CONFIG_ARCH_SH7377) || \
675 defined(CONFIG_ARCH_SH7372)
676#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
677#elif defined(CONFIG_CPU_SH7723) ||\
678 defined(CONFIG_CPU_SH7724)
Nobuhiro Iwamatsuf3038cd2010-11-24 13:42:13 +0900[diff] [blame]679static inline int scbrr_calc(struct uart_port port, int bps, int clk)
Nobuhiro Iwamatsu3f6c8e32010-10-26 03:55:15 +0900[diff] [blame]680{
Nobuhiro Iwamatsuf3038cd2010-11-24 13:42:13 +0900[diff] [blame]681 if (port.type == PORT_SCIF)
Nobuhiro Iwamatsu3f6c8e32010-10-26 03:55:15 +0900[diff] [blame]682 return (clk+16*bps)/(32*bps)-1;
683 else
684 return ((clk*2)+16*bps)/(16*bps)-1;
685}
Nobuhiro Iwamatsuf3038cd2010-11-24 13:42:13 +0900[diff] [blame]686#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
Nobuhiro Iwamatsu3f6c8e32010-10-26 03:55:15 +0900[diff] [blame]687#elif defined(__H8300H__) || defined(__H8300S__)
688#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
Phil Edworthy7fbeb642011-06-01 07:35:13 +0100[diff] [blame]689#elif defined(CONFIG_CPU_SH7264)
690#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps))
Nobuhiro Iwamatsu3f6c8e32010-10-26 03:55:15 +0900[diff] [blame]691#else /* Generic SH */
692#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
693#endif