blob: 851872ae3cfd0b538ce1762b550343537fae7e51 [file] [log] [blame]
Anton Vorontsovfab6f552008-01-09 20:57:47 +03001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
7 *
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
Anton Vorontsovfab6f552008-01-09 20:57:47 +030020/*
21 * High Level Configuration Options
22 */
23#define CONFIG_E300 1 /* E300 family */
24#define CONFIG_QE 1 /* Has QE */
Peter Tyser0f898602009-05-22 17:23:24 -050025#define CONFIG_MPC83xx 1 /* MPC83xx family */
Anton Vorontsovfab6f552008-01-09 20:57:47 +030026#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
27#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
28
Wolfgang Denk2ae18242010-10-06 09:05:45 +020029#define CONFIG_SYS_TEXT_BASE 0xFF800000
30
Anton Vorontsovfab6f552008-01-09 20:57:47 +030031/*
32 * System Clock Setup
33 */
34#ifdef CONFIG_CLKIN_33MHZ
Anton Vorontsovf700e7d2008-03-24 20:47:05 +030035#define CONFIG_83XX_CLKIN 33333333
36#define CONFIG_SYS_CLK_FREQ 33333333
Wolfgang Denk2ae18242010-10-06 09:05:45 +020037#define CONFIG_PCI_33M 1
Anton Vorontsovfab6f552008-01-09 20:57:47 +030038#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
39#else
40#define CONFIG_83XX_CLKIN 66000000
41#define CONFIG_SYS_CLK_FREQ 66000000
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_PCI_66M 1
Anton Vorontsovfab6f552008-01-09 20:57:47 +030043#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
44#endif /* CONFIG_CLKIN_33MHZ */
45
46/*
47 * Hardware Reset Configuration Word
48 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_HRCW_LOW (\
Anton Vorontsovfab6f552008-01-09 20:57:47 +030050 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
51 HRCWL_DDR_TO_SCB_CLK_1X1 |\
52 HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
53 HRCWL_CORE_TO_CSB_2X1 |\
54 HRCWL_CE_TO_PLL_1X15)
55
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_HRCW_HIGH (\
Anton Vorontsovfab6f552008-01-09 20:57:47 +030057 HRCWH_PCI_HOST |\
58 HRCWH_PCI1_ARBITER_ENABLE |\
59 HRCWH_PCICKDRV_ENABLE |\
60 HRCWH_CORE_ENABLE |\
61 HRCWH_FROM_0X00000100 |\
62 HRCWH_BOOTSEQ_DISABLE |\
63 HRCWH_SW_WATCHDOG_DISABLE |\
64 HRCWH_ROM_LOC_LOCAL_16BIT |\
65 HRCWH_SECONDARY_DDR_DISABLE |\
66 HRCWH_BIG_ENDIAN |\
67 HRCWH_LALE_EARLY)
68
69/*
70 * System IO Config
71 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_SICRH 0x00000000
73#define CONFIG_SYS_SICRL 0x40000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +030074
Anton Vorontsovfab6f552008-01-09 20:57:47 +030075#define CONFIG_BOARD_EARLY_INIT_R
76
77/*
78 * IMMR new address
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_IMMR 0xE0000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +030081
82/*
83 * DDR Setup
84 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
86#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
87#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
88#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +030089 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
90
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_83XX_DDR_USES_CS0
Anton Vorontsovfab6f552008-01-09 20:57:47 +030092
Anton Vorontsovd892b2d2008-03-24 20:46:57 +030093#define CONFIG_DDR_ECC /* support DDR ECC function */
94#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
Anton Vorontsovfab6f552008-01-09 20:57:47 +030095
96/*
97 * DDRCDR - DDR Control Driver Register
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300100
101#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
102
103/*
104 * Manually set up DDR parameters
105 */
106#define CONFIG_DDR_II
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_DDR_SIZE 256 /* MB */
108#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
109#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300110 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN)
112#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
113#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
114#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300115 (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_DDR_MODE 0x47800432
117#define CONFIG_SYS_DDR_MODE2 0x8000c000
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300120 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
121 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
122 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
123 (0 << TIMING_CFG0_WWT_SHIFT) | \
124 (0 << TIMING_CFG0_RRT_SHIFT) | \
125 (0 << TIMING_CFG0_WRT_SHIFT) | \
126 (0 << TIMING_CFG0_RWT_SHIFT))
127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_30) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300129 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
130 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
131 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
132 (10 << TIMING_CFG1_REFREC_SHIFT) | \
133 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
134 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
135 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
Anton Vorontsovd892b2d2008-03-24 20:46:57 +0300138 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
139 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
140 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
141 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
142 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
143 (0 << TIMING_CFG2_CPO_SHIFT))
144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300146
147/*
148 * Memory test
149 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
151#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
152#define CONFIG_SYS_MEMTEST_END 0x00100000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300153
154/*
155 * The reserved memory
156 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200157#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
161#define CONFIG_SYS_RAMBOOT
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300162#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#undef CONFIG_SYS_RAMBOOT
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300164#endif
165
Anatolij Gustschin8e150882009-04-23 21:29:34 +0200166#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300168
169/*
170 * Initial RAM Base Address Setup
171 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_INIT_RAM_LOCK 1
173#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200174#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200175#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300176
177/*
178 * Local Bus Configuration & Clock Setup
179 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500180#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
181#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_LBC_LBCR 0x00000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300183
184/*
185 * FLASH on the Local Bus
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200188#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
190#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
193#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300196 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
197 BR_V) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400199 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300200 OR_GPCM_XACS | OR_GPCM_SCY_15 | \
201 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
204#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#undef CONFIG_SYS_FLASH_CHECKSUM
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300207
208/*
209 * NAND flash on the local bus
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_NAND_BASE 0x60000000
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300212#define CONFIG_CMD_NAND 1
213#define CONFIG_NAND_FSL_UPM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_MAX_NAND_DEVICE 1
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300215#define CONFIG_MTD_NAND_VERIFY_WRITE
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
218#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300219
220/* Port size 8 bit, UPMA */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | 0x00000881)
222#define CONFIG_SYS_OR1_PRELIM 0xfc000001
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300223
224/*
225 * Fujitsu MB86277 (MINT) graphics controller
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_VIDEO_BASE 0x70000000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE
230#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300231
232/* Port size 32 bit, UPMB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
234#define CONFIG_SYS_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300235
236/*
237 * Serial Port
238 */
239#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_NS16550
241#define CONFIG_SYS_NS16550_SERIAL
242#define CONFIG_SYS_NS16550_REG_SIZE 1
243#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_BAUDRATE_TABLE \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300246 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
249#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300250
251#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500252#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300253/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_HUSH_PARSER
255#ifdef CONFIG_SYS_HUSH_PARSER
256#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300257#endif
258
259/* Pass open firmware flat tree */
260#define CONFIG_OF_LIBFDT 1
261#define CONFIG_OF_BOARD_SETUP 1
Anton Vorontsov3a0cfdd2008-03-24 20:47:02 +0300262#define CONFIG_OF_STDOUT_VIA_ALIAS
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300263
264/* I2C */
265#define CONFIG_HARD_I2C /* I2C with hardware support */
266#undef CONFIG_SOFT_I2C /* I2C bit-banged */
267#define CONFIG_FSL_I2C
268#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
270#define CONFIG_SYS_I2C_SLAVE 0x7F
271#define CONFIG_SYS_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */
272#define CONFIG_SYS_I2C_OFFSET 0x3000
273#define CONFIG_SYS_I2C2_OFFSET 0x3100
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300274
275/*
276 * General PCI
277 * Addresses are mapped 1-1.
278 */
279#define CONFIG_PCI
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
282#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
283#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
284#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
285#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
286#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
287#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
288#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
289#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300290
291#ifdef CONFIG_PCI
292
293#define CONFIG_NET_MULTI
294#define CONFIG_PCI_PNP /* do pci plug-and-play */
295
296#undef CONFIG_EEPRO100
297#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300299
300#endif /* CONFIG_PCI */
301
302
303#ifndef CONFIG_NET_MULTI
304#define CONFIG_NET_MULTI 1
305#endif
306
307/*
308 * QE UEC ethernet configuration
309 */
310#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500311#define CONFIG_ETHPRIME "UEC0"
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300312
313#define CONFIG_UEC_ETH1 /* GETH1 */
314
315#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
317#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
318#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
319#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
320#define CONFIG_SYS_UEC1_PHY_ADDR 2
Andy Fleming865ff852011-04-13 00:37:12 -0500321#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100322#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300323#endif
324
325#define CONFIG_UEC_ETH2 /* GETH2 */
326
327#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
329#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
330#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
331#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
332#define CONFIG_SYS_UEC2_PHY_ADDR 4
Andy Fleming865ff852011-04-13 00:37:12 -0500333#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
Heiko Schocher582c55a2010-01-20 09:04:28 +0100334#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300335#endif
336
337/*
338 * Environment
339 */
340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200342#define CONFIG_ENV_IS_IN_FLASH 1
Anatolij Gustschin8e150882009-04-23 21:29:34 +0200343#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200344#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
345#define CONFIG_ENV_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#else /* CONFIG_SYS_RAMBOOT */
347#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200348#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200350#define CONFIG_ENV_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#endif /* CONFIG_SYS_RAMBOOT */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300352
353#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300355
356/*
357 * BOOTP options
358 */
359#define CONFIG_BOOTP_BOOTFILESIZE
360#define CONFIG_BOOTP_BOOTPATH
361#define CONFIG_BOOTP_GATEWAY
362#define CONFIG_BOOTP_HOSTNAME
363
364
365/*
366 * Command line configuration.
367 */
368#include <config_cmd_default.h>
369
370#define CONFIG_CMD_PING
371#define CONFIG_CMD_I2C
372#define CONFIG_CMD_ASKENV
Anton Vorontsov3419eb62008-03-24 20:47:00 +0300373#define CONFIG_CMD_DHCP
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300374
375#if defined(CONFIG_PCI)
376#define CONFIG_CMD_PCI
377#endif
378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500380#undef CONFIG_CMD_SAVEENV
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300381#undef CONFIG_CMD_LOADS
382#endif
383
384#undef CONFIG_WATCHDOG /* watchdog disabled */
385
386/*
387 * Miscellaneous configurable options
388 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_LONGHELP /* undef to save memory */
390#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
391#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300392
393#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300395#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300397#endif
398
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
400#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
401#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
402#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300403
404/*
405 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700406 * have to be in the first 256 MB of memory, since this is
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300407 * the maximum mapped by the Linux kernel during initialization.
408 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700409#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300410
411/*
412 * Core HID Setup
413 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500414#define CONFIG_SYS_HID0_INIT 0x000000000
415#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
416 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_HID2 HID2_HBE
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300418
419/*
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300420 * MMU Setup
421 */
422
Becky Bruce31d82672008-05-08 19:02:12 -0500423#define CONFIG_HIGH_BATS 1 /* High BATs supported */
424
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300425/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
427#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
428#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
429#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300430
431/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300433 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
435#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
436#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300437
438/* NAND: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300440 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
442#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
443#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300444
445/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
447#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
448#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300449 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300451
452/* Stack in dcache: cacheable, no memory coherence */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
454#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
455#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
456#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300457
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300459 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
461#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
462#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300463
464#ifdef CONFIG_PCI
465/* PCI MEM space: cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
467#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
468#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
469#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300470/* PCI MMIO space: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300472 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
474#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
475#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300476#else /* CONFIG_PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_IBAT6L (0)
478#define CONFIG_SYS_IBAT6U (0)
479#define CONFIG_SYS_IBAT7L (0)
480#define CONFIG_SYS_IBAT7U (0)
481#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
482#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
483#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
484#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300485#endif /* CONFIG_PCI */
486
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300487#if defined(CONFIG_CMD_KGDB)
488#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
489#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
490#endif
491
492/*
493 * Environment Configuration
494 */
495#define CONFIG_ENV_OVERWRITE
496
497#if defined(CONFIG_UEC_ETH)
498#define CONFIG_HAS_ETH0
499#define CONFIG_HAS_ETH1
500#define CONFIG_HAS_ETH2
501#define CONFIG_HAS_ETH3
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300502#endif
503
504#define CONFIG_BAUDRATE 115200
505
506#define CONFIG_LOADADDR a00000
507#define CONFIG_HOSTNAME mpc8360erdk
508#define CONFIG_BOOTFILE uImage
509
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300510#define CONFIG_ROOTPATH /nfsroot/
511
512#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
513#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
514
515#define CONFIG_EXTRA_ENV_SETTINGS \
516 "netdev=eth0\0"\
517 "consoledev=ttyS0\0"\
518 "loadaddr=a00000\0"\
519 "fdtaddr=900000\0"\
Kim Phillipscc861f72009-08-26 21:25:46 -0500520 "fdtfile=mpc836x_rdk.dtb\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300521 "fsfile=fs\0"\
522 "ubootfile=u-boot.bin\0"\
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300523 "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300524 "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200525 "$mtdparts panic=1\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300526 "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
527 "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200528 "$gatewayip:$netmask:$hostname:$netdev:off "\
529 "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300530 "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\
531 "rootfstype=jffs2 rw\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300532 "tftp_get_uboot=tftp 100000 $ubootfile\0"\
533 "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
534 "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
535 "tftp_get_fs=tftp c00000 $fsfile\0"\
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300536 "nand_erase_kernel=nand erase 0 400000\0"\
537 "nand_erase_dtb=nand erase 400000 20000\0"\
538 "nand_erase_fs=nand erase 420000 3be0000\0"\
539 "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\
540 "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\
541 "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\
542 "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\
543 "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300544 "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200545 "cp.b 100000 ff800000 $filesize\0"\
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300546 "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\
547 "nand_write_kernel\0"\
548 "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
549 "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\
550 "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\
551 "nand_reflash_fs\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300552 "boot_m=bootm $loadaddr - $fdtaddr\0"\
Anton Vorontsov3419eb62008-03-24 20:47:00 +0300553 "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300554 "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
Anton Vorontsov3419eb62008-03-24 20:47:00 +0300555 "boot_m\0"\
Anton Vorontsov7ad95942008-03-24 20:46:51 +0300556 "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
557 "boot_m\0"\
Anton Vorontsovfab6f552008-01-09 20:57:47 +0300558 ""
559
560#define CONFIG_BOOTCOMMAND "run dhcpboot"
561
562#endif /* __CONFIG_H */