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Lei Wenaf62a552011-06-28 21:50:06 +00001/*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * Back ported to the 8xx platform (from the 8260 platform) by
24 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
25 */
26#ifndef __SDHCI_HW_H
27#define __SDHCI_HW_H
28
29#include <asm/io.h>
30/*
31 * Controller registers
32 */
33
34#define SDHCI_DMA_ADDRESS 0x00
35
36#define SDHCI_BLOCK_SIZE 0x04
37#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
38
39#define SDHCI_BLOCK_COUNT 0x06
40
41#define SDHCI_ARGUMENT 0x08
42
43#define SDHCI_TRANSFER_MODE 0x0C
44#define SDHCI_TRNS_DMA 0x01
45#define SDHCI_TRNS_BLK_CNT_EN 0x02
46#define SDHCI_TRNS_ACMD12 0x04
47#define SDHCI_TRNS_READ 0x10
48#define SDHCI_TRNS_MULTI 0x20
49
50#define SDHCI_COMMAND 0x0E
51#define SDHCI_CMD_RESP_MASK 0x03
52#define SDHCI_CMD_CRC 0x08
53#define SDHCI_CMD_INDEX 0x10
54#define SDHCI_CMD_DATA 0x20
55#define SDHCI_CMD_ABORTCMD 0xC0
56
57#define SDHCI_CMD_RESP_NONE 0x00
58#define SDHCI_CMD_RESP_LONG 0x01
59#define SDHCI_CMD_RESP_SHORT 0x02
60#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
61
62#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
63#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
64
65#define SDHCI_RESPONSE 0x10
66
67#define SDHCI_BUFFER 0x20
68
69#define SDHCI_PRESENT_STATE 0x24
70#define SDHCI_CMD_INHIBIT 0x00000001
71#define SDHCI_DATA_INHIBIT 0x00000002
72#define SDHCI_DOING_WRITE 0x00000100
73#define SDHCI_DOING_READ 0x00000200
74#define SDHCI_SPACE_AVAILABLE 0x00000400
75#define SDHCI_DATA_AVAILABLE 0x00000800
76#define SDHCI_CARD_PRESENT 0x00010000
77#define SDHCI_WRITE_PROTECT 0x00080000
78
79#define SDHCI_HOST_CONTROL 0x28
80#define SDHCI_CTRL_LED 0x01
81#define SDHCI_CTRL_4BITBUS 0x02
82#define SDHCI_CTRL_HISPD 0x04
83#define SDHCI_CTRL_DMA_MASK 0x18
84#define SDHCI_CTRL_SDMA 0x00
85#define SDHCI_CTRL_ADMA1 0x08
86#define SDHCI_CTRL_ADMA32 0x10
87#define SDHCI_CTRL_ADMA64 0x18
88#define SDHCI_CTRL_8BITBUS 0x20
89
90#define SDHCI_POWER_CONTROL 0x29
91#define SDHCI_POWER_ON 0x01
92#define SDHCI_POWER_180 0x0A
93#define SDHCI_POWER_300 0x0C
94#define SDHCI_POWER_330 0x0E
95
96#define SDHCI_BLOCK_GAP_CONTROL 0x2A
97
98#define SDHCI_WAKE_UP_CONTROL 0x2B
99#define SDHCI_WAKE_ON_INT 0x01
100#define SDHCI_WAKE_ON_INSERT 0x02
101#define SDHCI_WAKE_ON_REMOVE 0x04
102
103#define SDHCI_CLOCK_CONTROL 0x2C
104#define SDHCI_DIVIDER_SHIFT 8
105#define SDHCI_DIVIDER_HI_SHIFT 6
106#define SDHCI_DIV_MASK 0xFF
107#define SDHCI_DIV_MASK_LEN 8
108#define SDHCI_DIV_HI_MASK 0x300
109#define SDHCI_CLOCK_CARD_EN 0x0004
110#define SDHCI_CLOCK_INT_STABLE 0x0002
111#define SDHCI_CLOCK_INT_EN 0x0001
112
113#define SDHCI_TIMEOUT_CONTROL 0x2E
114
115#define SDHCI_SOFTWARE_RESET 0x2F
116#define SDHCI_RESET_ALL 0x01
117#define SDHCI_RESET_CMD 0x02
118#define SDHCI_RESET_DATA 0x04
119
120#define SDHCI_INT_STATUS 0x30
121#define SDHCI_INT_ENABLE 0x34
122#define SDHCI_SIGNAL_ENABLE 0x38
123#define SDHCI_INT_RESPONSE 0x00000001
124#define SDHCI_INT_DATA_END 0x00000002
125#define SDHCI_INT_DMA_END 0x00000008
126#define SDHCI_INT_SPACE_AVAIL 0x00000010
127#define SDHCI_INT_DATA_AVAIL 0x00000020
128#define SDHCI_INT_CARD_INSERT 0x00000040
129#define SDHCI_INT_CARD_REMOVE 0x00000080
130#define SDHCI_INT_CARD_INT 0x00000100
131#define SDHCI_INT_ERROR 0x00008000
132#define SDHCI_INT_TIMEOUT 0x00010000
133#define SDHCI_INT_CRC 0x00020000
134#define SDHCI_INT_END_BIT 0x00040000
135#define SDHCI_INT_INDEX 0x00080000
136#define SDHCI_INT_DATA_TIMEOUT 0x00100000
137#define SDHCI_INT_DATA_CRC 0x00200000
138#define SDHCI_INT_DATA_END_BIT 0x00400000
139#define SDHCI_INT_BUS_POWER 0x00800000
140#define SDHCI_INT_ACMD12ERR 0x01000000
141#define SDHCI_INT_ADMA_ERROR 0x02000000
142
143#define SDHCI_INT_NORMAL_MASK 0x00007FFF
144#define SDHCI_INT_ERROR_MASK 0xFFFF8000
145
146#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
147 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
148#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
149 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
150 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
151 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
152#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
153
154#define SDHCI_ACMD12_ERR 0x3C
155
156/* 3E-3F reserved */
157
158#define SDHCI_CAPABILITIES 0x40
159#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
160#define SDHCI_TIMEOUT_CLK_SHIFT 0
161#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
162#define SDHCI_CLOCK_BASE_MASK 0x00003F00
163#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
164#define SDHCI_CLOCK_BASE_SHIFT 8
165#define SDHCI_MAX_BLOCK_MASK 0x00030000
166#define SDHCI_MAX_BLOCK_SHIFT 16
167#define SDHCI_CAN_DO_8BIT 0x00040000
168#define SDHCI_CAN_DO_ADMA2 0x00080000
169#define SDHCI_CAN_DO_ADMA1 0x00100000
170#define SDHCI_CAN_DO_HISPD 0x00200000
171#define SDHCI_CAN_DO_SDMA 0x00400000
172#define SDHCI_CAN_VDD_330 0x01000000
173#define SDHCI_CAN_VDD_300 0x02000000
174#define SDHCI_CAN_VDD_180 0x04000000
175#define SDHCI_CAN_64BIT 0x10000000
176
177#define SDHCI_CAPABILITIES_1 0x44
178
179#define SDHCI_MAX_CURRENT 0x48
180
181/* 4C-4F reserved for more max current */
182
183#define SDHCI_SET_ACMD12_ERROR 0x50
184#define SDHCI_SET_INT_ERROR 0x52
185
186#define SDHCI_ADMA_ERROR 0x54
187
188/* 55-57 reserved */
189
190#define SDHCI_ADMA_ADDRESS 0x58
191
192/* 60-FB reserved */
193
194#define SDHCI_SLOT_INT_STATUS 0xFC
195
196#define SDHCI_HOST_VERSION 0xFE
197#define SDHCI_VENDOR_VER_MASK 0xFF00
198#define SDHCI_VENDOR_VER_SHIFT 8
199#define SDHCI_SPEC_VER_MASK 0x00FF
200#define SDHCI_SPEC_VER_SHIFT 0
201#define SDHCI_SPEC_100 0
202#define SDHCI_SPEC_200 1
203#define SDHCI_SPEC_300 2
204
205/*
206 * End of controller registers.
207 */
208
209#define SDHCI_MAX_DIV_SPEC_200 256
210#define SDHCI_MAX_DIV_SPEC_300 2046
211
212/*
213 * quirks
214 */
215#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
216
217/*
218 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
219 */
220#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
221#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
222struct sdhci_ops {
223#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
224 u32 (*read_l)(struct sdhci_host *host, int reg);
225 u16 (*read_w)(struct sdhci_host *host, int reg);
226 u8 (*read_b)(struct sdhci_host *host, int reg);
227 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
228 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
229 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
230#endif
231};
232
233struct sdhci_host {
234 char *name;
235 void *ioaddr;
236 unsigned int quirks;
237 unsigned int version;
238 unsigned int clock;
239 const struct sdhci_ops *ops;
240};
241
242#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
243
244static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
245{
246 if (unlikely(host->ops->write_l))
247 host->ops->write_l(host, val, reg);
248 else
249 writel(val, host->ioaddr + reg);
250}
251
252static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
253{
254 if (unlikely(host->ops->write_w))
255 host->ops->write_w(host, val, reg);
256 else
257 writew(val, host->ioaddr + reg);
258}
259
260static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
261{
262 if (unlikely(host->ops->write_b))
263 host->ops->write_b(host, val, reg);
264 else
265 writeb(val, host->ioaddr + reg);
266}
267
268static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
269{
270 if (unlikely(host->ops->read_l))
271 return host->ops->read_l(host, reg);
272 else
273 return readl(host->ioaddr + reg);
274}
275
276static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
277{
278 if (unlikely(host->ops->read_w))
279 return host->ops->read_w(host, reg);
280 else
281 return readw(host->ioaddr + reg);
282}
283
284static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
285{
286 if (unlikely(host->ops->read_b))
287 return host->ops->read_b(host, reg);
288 else
289 return readb(host->ioaddr + reg);
290}
291
292#else
293
294static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
295{
296 writel(val, host->ioaddr + reg);
297}
298
299static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
300{
301 writew(val, host->ioaddr + reg);
302}
303
304static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
305{
306 writeb(val, host->ioaddr + reg);
307}
308static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
309{
310 return readl(host->ioaddr + reg);
311}
312
313static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
314{
315 return readw(host->ioaddr + reg);
316}
317
318static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
319{
320 return readb(host->ioaddr + reg);
321}
322#endif
323
324int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk);
325#endif /* __SDHCI_HW_H */