blob: 506b783d34e6bf0e1488044b813be21a73493d17 [file] [log] [blame]
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +09001/*
2 * include/configs/blanche.h
3 * This file is blanche board configuration.
4 *
5 * Copyright (C) 2016 Renesas Electronics Corporation
6 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#ifndef __BLANCHE_H
11#define __BLANCHE_H
12
13#undef DEBUG
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090014#define CONFIG_RMOBILE_BOARD_STRING "Blanche"
15
16#include "rcar-gen2-common.h"
17
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090018/* STACK */
19#define CONFIG_SYS_INIT_SP_ADDR 0xE817FFFC
20#define STACK_AREA_SIZE 0xC000
21#define LOW_LEVEL_MERAM_STACK \
22 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
23
24/* MEMORY */
25#define RCAR_GEN2_SDRAM_BASE 0x40000000
26#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
27#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
28
29/* SCIF */
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090030#define CONFIG_CONS_SCIF0
31
32#define CONFIG_SYS_MEMTEST_START (RCAR_GEN2_SDRAM_BASE)
33#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 504 * 1024 * 1024)
34
35#undef CONFIG_SYS_ALT_MEMTEST
36#undef CONFIG_SYS_MEMTEST_SCRATCH
37#undef CONFIG_SYS_LOADS_BAUD_CHANGE
38
39/* FLASH */
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090040#if !defined(CONFIG_MTD_NOR_FLASH)
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090041#define CONFIG_SPI
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090042#define CONFIG_SH_QSPI_BASE 0xE6B10000
43#else
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090044#define CONFIG_SYS_FLASH_CFI
45#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
46#define CONFIG_FLASH_CFI_DRIVER
47#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
48#define CONFIG_FLASH_SHOW_PROGRESS 45
49#define CONFIG_SYS_FLASH_BASE 0x00000000
50#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
51#define CONFIG_SYS_MAX_FLASH_SECT 1024
52#define CONFIG_SYS_MAX_FLASH_BANKS 1
53#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
54#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
55
56#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
57#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
58#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
59#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090060#undef CONFIG_CMD_SF
61#undef CONFIG_CMD_SPI
62#endif
63
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090064
65/* Board Clock */
66#define RMOBILE_XTAL_CLK 20000000u
67#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
68#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
69#define CONFIG_SYS_TMU_CLK_DIV 4
70
71/* ENV setting */
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090072#if !defined(CONFIG_MTD_NOR_FLASH)
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090073#else
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090074#undef CONFIG_ENV_ADDR
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090075#define CONFIG_ENV_SECT_SIZE (256 * 1024)
76#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
77#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
78#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
79#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
80#endif
81
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090082/* Module stop status bits */
83/* INTC-RT */
84#define CONFIG_SMSTP0_ENA 0x00400000
85/* SDHI0 */
86#define CONFIG_SMSTP3_ENA 0x00004000
87/* INTC-SYS, IRQC */
88#define CONFIG_SMSTP4_ENA 0x00000180
89/* SCIF0 */
90#define CONFIG_SMSTP7_ENA 0x00200000
91/* QSPI */
92#define CONFIG_SMSTP9_ENA 0x00020000
93/* SYS-DMAC0 */
94#define CONFIG_RMSTP2_ENA 0x00080000
95
96/* SDHI */
97#define CONFIG_SH_SDHI_FREQ 97500000
masakazu.mochizuki.wd@hitachi.com6f107e42016-04-12 17:11:41 +090098
99#endif /* __BLANCHE_H */