blob: 5610644d79b15d968166c2eb76bca7055610637d [file] [log] [blame]
Michael Schwingenbc243452008-01-16 19:51:55 +01001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
25OUTPUT_ARCH (arm)
26ENTRY (_start)
27SECTIONS
28{
29 . = 0x00000000;
30
31 . = ALIGN (4);
32 .text : {
Albert ARIBAUDd026dec2013-06-11 14:17:33 +020033 *(.__image_copy_start)
Michael Schwingen8b5ab4c2011-05-23 00:00:06 +020034 arch/arm/cpu/ixp/start.o(.text*)
35 net/libnet.o(.text*)
36 board/actux3/libactux3.o(.text*)
37 arch/arm/cpu/ixp/libixp.o(.text*)
Tom Rini1fb187b2012-10-17 10:18:29 +000038 drivers/input/libinput.o(.text*)
Michael Schwingenbc243452008-01-16 19:51:55 +010039
40 . = env_offset;
Michael Schwingen8b5ab4c2011-05-23 00:00:06 +020041 common/env_embedded.o(.ppcenv)
42 *(.text*)
Michael Schwingenbc243452008-01-16 19:51:55 +010043 }
44
Michael Schwingen8b5ab4c2011-05-23 00:00:06 +020045 . = ALIGN(4);
Michael Schwingenbc243452008-01-16 19:51:55 +010046 .rodata : {
Trent Piephof62fb992009-02-18 15:22:05 -080047 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
Michael Schwingenbc243452008-01-16 19:51:55 +010048 }
Michael Schwingen8b5ab4c2011-05-23 00:00:06 +020049 . = ALIGN(4);
Michael Schwingenbc243452008-01-16 19:51:55 +010050 .data : {
Michael Schwingen8b5ab4c2011-05-23 00:00:06 +020051 *(.data*)
Michael Schwingenbc243452008-01-16 19:51:55 +010052 }
Michael Schwingen8b5ab4c2011-05-23 00:00:06 +020053 . = ALIGN(4);
Michael Schwingenbc243452008-01-16 19:51:55 +010054 .got : {
55 *(.got)
56 }
Michael Schwingenbc243452008-01-16 19:51:55 +010057 . =.;
Michael Schwingenbc243452008-01-16 19:51:55 +010058
Marek Vasut55675142012-10-12 10:27:03 +000059 . = ALIGN(4);
60 .u_boot_list : {
Albert ARIBAUDef123c52013-02-25 00:59:00 +000061 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut55675142012-10-12 10:27:03 +000062 }
63
Michael Schwingenbc243452008-01-16 19:51:55 +010064 . = ALIGN (4);
Benoît Thébaudeau7086e912013-04-11 09:35:46 +000065
Albert ARIBAUDd026dec2013-06-11 14:17:33 +020066 .image_copy_end :
67 {
68 *(.__image_copy_end)
69 }
Benoît Thébaudeau7086e912013-04-11 09:35:46 +000070
Albert ARIBAUD47bd65e2013-06-11 14:17:34 +020071 .rel_dyn_start :
72 {
73 *(.__rel_dyn_start)
74 }
75
Michael Schwingen8b5ab4c2011-05-23 00:00:06 +020076 .rel.dyn : {
Michael Schwingen8b5ab4c2011-05-23 00:00:06 +020077 *(.rel*)
Albert ARIBAUD47bd65e2013-06-11 14:17:34 +020078 }
79
80 .rel_dyn_end :
81 {
82 *(.__rel_dyn_end)
Michael Schwingen8b5ab4c2011-05-23 00:00:06 +020083 }
84
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000085 _end = .;
86
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000087/*
88 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
89 * __bss_base and __bss_limit are for linker only (overlay ordering)
90 */
91
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000092 .bss_start __rel_dyn_start (OVERLAY) : {
93 KEEP(*(.__bss_start));
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000094 __bss_base = .;
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000095 }
96
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000097 .bss __bss_base (OVERLAY) : {
Michael Schwingen8b5ab4c2011-05-23 00:00:06 +020098 *(.bss*)
99 . = ALIGN(4);
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000100 __bss_limit = .;
Michael Schwingenbc243452008-01-16 19:51:55 +0100101 }
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000102 .bss_end __bss_limit (OVERLAY) : {
103 KEEP(*(.__bss_end));
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000104 }
105
Albert ARIBAUD09d81182013-06-11 14:17:31 +0200106 /DISCARD/ : { *(.dynsym) }
Michael Schwingen8b5ab4c2011-05-23 00:00:06 +0200107 /DISCARD/ : { *(.dynstr*) }
108 /DISCARD/ : { *(.dynamic*) }
109 /DISCARD/ : { *(.plt*) }
110 /DISCARD/ : { *(.interp*) }
111 /DISCARD/ : { *(.gnu*) }
Michael Schwingenbc243452008-01-16 19:51:55 +0100112}