blob: f5ac32a332246fe2b7be3d1881cb5facc0b450d5 [file] [log] [blame]
Holger Brunck0f2b7212012-03-21 13:42:46 +01001/*
2 * (C) Copyright 2012
3 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
4 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Holger Brunck0f2b7212012-03-21 13:42:46 +01007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/* KMBEC FPGA (PRIO) */
13#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
14#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
15
16#if defined CONFIG_KMETER1
17#define CONFIG_HOSTNAME kmeter1
18#define CONFIG_KM_BOARD_NAME "kmeter1"
19#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
20#elif defined CONFIG_KMCOGE5NE
21#define CONFIG_HOSTNAME kmcoge5ne
22#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
23#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
24#define CONFIG_CMD_NAND
Holger Brunckbe7576f2013-01-21 03:55:23 +000025#define CONFIG_NAND_ECC_BCH
26#define CONFIG_BCH
Holger Brunck0f2b7212012-03-21 13:42:46 +010027#define CONFIG_NAND_KMETER1
28#define CONFIG_SYS_MAX_NAND_DEVICE 1
29#define NAND_MAX_CHIPS 1
30#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
31
32#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
33#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
34#define MTDIDS_DEFAULT "nor0=boot,nand0=app"
35
36#define MTDPARTS_DEFAULT "mtdparts=" \
37 "boot:" \
38 "768k(u-boot)," \
39 "128k(env)," \
40 "128k(envred)," \
41 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" \
42 "app:" \
43 "-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");"
44#else
45#error ("Board not supported")
46#endif
47
48/*
49 * High Level Configuration Options
50 */
51#define CONFIG_QE /* Has QE */
52#define CONFIG_MPC8360 /* MPC8360 CPU specific */
53
54#define CONFIG_SYS_TEXT_BASE 0xF0000000
55
56/* include common defines/options for all 83xx Keymile boards */
57#include "km/km83xx-common.h"
58
59/*
60 * System IO Setup
61 */
62#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
63
64/*
65 * Hardware Reset Configuration Word
66 */
67#define CONFIG_SYS_HRCW_LOW (\
68 HRCWL_CSB_TO_CLKIN_4X1 | \
69 HRCWL_CORE_TO_CSB_2X1 | \
70 HRCWL_CE_PLL_VCO_DIV_2 | \
71 HRCWL_CE_TO_PLL_1X6)
72
73#define CONFIG_SYS_HRCW_HIGH (\
74 HRCWH_CORE_ENABLE | \
75 HRCWH_FROM_0X00000100 | \
76 HRCWH_BOOTSEQ_DISABLE | \
77 HRCWH_SW_WATCHDOG_DISABLE | \
78 HRCWH_ROM_LOC_LOCAL_16BIT | \
79 HRCWH_BIG_ENDIAN | \
80 HRCWH_LALE_EARLY | \
81 HRCWH_LDP_CLEAR)
82
83/**
84 * DDR RAM settings
85 */
86#define CONFIG_SYS_DDR_SDRAM_CFG (\
87 SDRAM_CFG_SDRAM_TYPE_DDR2 | \
88 SDRAM_CFG_SREN | \
89 SDRAM_CFG_HSE)
90
91#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
92
93#ifdef CONFIG_KMCOGE5NE
94/**
95 * KMCOGE5NE has 512 MB RAM
96 */
97#define CONFIG_SYS_DDR_CS0_CONFIG (\
98 CSCONFIG_EN | \
99 CSCONFIG_AP | \
100 CSCONFIG_ODT_RD_ONLY_CURRENT | \
101 CSCONFIG_BANK_BIT_3 | \
102 CSCONFIG_ROW_BIT_13 | \
103 CSCONFIG_COL_BIT_10)
104#else
105#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
106 CSCONFIG_ROW_BIT_13 | \
107 CSCONFIG_COL_BIT_10 | \
108 CSCONFIG_ODT_RD_ONLY_CURRENT)
109#endif
110
111#define CONFIG_SYS_DDR_CLK_CNTL (\
112 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
113
114#define CONFIG_SYS_DDR_INTERVAL (\
115 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
116 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
117
118#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
119
120#define CONFIG_SYS_DDRCDR (\
121 DDRCDR_EN | \
122 DDRCDR_Q_DRN)
123#define CONFIG_SYS_DDR_MODE 0x47860452
124#define CONFIG_SYS_DDR_MODE2 0x8080c000
125
126#define CONFIG_SYS_DDR_TIMING_0 (\
127 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
128 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
129 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
130 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
131 (0 << TIMING_CFG0_WWT_SHIFT) | \
132 (0 << TIMING_CFG0_RRT_SHIFT) | \
133 (0 << TIMING_CFG0_WRT_SHIFT) | \
134 (0 << TIMING_CFG0_RWT_SHIFT))
135
136#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
137 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
138 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
139 (3 << TIMING_CFG1_WRREC_SHIFT) | \
140 (7 << TIMING_CFG1_REFREC_SHIFT) | \
141 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
142 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
143 (3 << TIMING_CFG1_PRETOACT_SHIFT))
144
145#define CONFIG_SYS_DDR_TIMING_2 (\
146 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
147 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
148 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
149 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
150 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
151 (5 << TIMING_CFG2_CPO_SHIFT) | \
152 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
153
154#define CONFIG_SYS_DDR_TIMING_3 0x00000000
155
156/* EEprom support */
157#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
158
159/*
160 * Local Bus Configuration & Clock Setup
161 */
162#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
163#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
164#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
165
166/*
167 * PAXE on the local bus CS3
168 */
169#define CONFIG_SYS_PAXE_BASE 0xA0000000
170#define CONFIG_SYS_PAXE_SIZE 256
171
172#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
173
174#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
175
176#define CONFIG_SYS_BR3_PRELIM (\
177 CONFIG_SYS_PAXE_BASE | \
178 (1 << BR_PS_SHIFT) | \
179 BR_V)
180
181#define CONFIG_SYS_OR3_PRELIM (\
182 MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
183 OR_GPCM_CSNT | \
184 OR_GPCM_ACS_DIV2 | \
185 OR_GPCM_SCY_2 | \
186 OR_GPCM_TRLX | \
187 OR_GPCM_EAD)
188
189#ifdef CONFIG_KMCOGE5NE
190/*
191 * BFTIC3 on the local bus CS4
192 */
193#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
194#define CONFIG_SYS_BFTIC3_SIZE 256
195
196#define CONFIG_SYS_BR4_PRELIM (\
197 CONFIG_SYS_BFTIC3_BASE |\
198 (1 << BR_PS_SHIFT) | \
199 BR_V)
200
201#define CONFIG_SYS_OR4_PRELIM (\
202 MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
203 OR_GPCM_CSNT | \
204 OR_GPCM_ACS_DIV2 |\
205 OR_GPCM_SCY_2 |\
206 OR_GPCM_TRLX |\
207 OR_GPCM_EAD)
208#endif
209
210/*
211 * MMU Setup
212 */
213
214/* PAXE: icache cacheable, but dcache-inhibit and guarded */
215#define CONFIG_SYS_IBAT5L (\
216 CONFIG_SYS_PAXE_BASE | \
217 BATL_PP_10 | \
218 BATL_MEMCOHERENCE)
219
220#define CONFIG_SYS_IBAT5U (\
221 CONFIG_SYS_PAXE_BASE | \
222 BATU_BL_256M | \
223 BATU_VS | \
224 BATU_VP)
225
226#define CONFIG_SYS_DBAT5L (\
227 CONFIG_SYS_PAXE_BASE | \
228 BATL_PP_10 | \
229 BATL_CACHEINHIBIT | \
230 BATL_GUARDEDSTORAGE)
231
232#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
233
234
235#ifdef CONFIG_KMCOGE5NE
236/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
237#define CONFIG_SYS_IBAT6L (\
238 CONFIG_SYS_BFTIC3_BASE | \
239 BATL_PP_10 | \
240 BATL_MEMCOHERENCE)
241
242#define CONFIG_SYS_IBAT6U (\
243 CONFIG_SYS_BFTIC3_BASE | \
244 BATU_BL_256M | \
245 BATU_VS | \
246 BATU_VP)
247
248#define CONFIG_SYS_DBAT6L (\
249 CONFIG_SYS_BFTIC3_BASE | \
250 BATL_PP_10 | \
251 BATL_CACHEINHIBIT | \
252 BATL_GUARDEDSTORAGE)
253
254#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
255
256/* DDR/LBC SDRAM next 256M: cacheable */
257#define CONFIG_SYS_IBAT7L (\
258 CONFIG_SYS_SDRAM_BASE2 |\
259 BATL_PP_10 |\
260 BATL_CACHEINHIBIT |\
261 BATL_GUARDEDSTORAGE)
262
263#define CONFIG_SYS_IBAT7U (\
264 CONFIG_SYS_SDRAM_BASE2 |\
265 BATU_BL_256M |\
266 BATU_VS |\
267 BATU_VP)
Thomas Herzmann95209b62012-05-04 10:55:56 +0200268/* enable POST tests */
269#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
270#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
271#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
272#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
273#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
274#define CONFIG_CMD_DIAG /* so that testpin is inquired for POST test */
275
Holger Brunck0f2b7212012-03-21 13:42:46 +0100276#else
277#define CONFIG_SYS_IBAT6L (0)
278#define CONFIG_SYS_IBAT6U (0)
279#define CONFIG_SYS_IBAT7L (0)
280#define CONFIG_SYS_IBAT7U (0)
281#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
282#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
283#endif
284
285#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
286#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
287
288#endif /* CONFIG */