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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 48041365b3420589ad464ebc7752e0053538b729 / . / include / configs / MPC8360EMDS.h
blob: 330c3073d221e710713e144d7beb4c23584323c7 [file] [log] [blame]
Dave Liu5f820432006-11-03 19:33:44 -0600[diff] [blame]1/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25#undef DEBUG
26
27/*
28 * High Level Configuration Options
29 */
30#define CONFIG_E300 1 /* E300 family */
31#define CONFIG_QE 1 /* Has QE */
32#define CONFIG_MPC83XX 1 /* MPC83XX family */
33#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
34#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
35
36/*
37 * System Clock Setup
38 */
39#ifdef CONFIG_PCISLAVE
40#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
41#else
42#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
43#endif
44
45#ifndef CONFIG_SYS_CLK_FREQ
46#define CONFIG_SYS_CLK_FREQ 66000000
47#endif
48
49/*
50 * Hardware Reset Configuration Word
51 */
52#define CFG_HRCW_LOW (\
53 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
54 HRCWL_DDR_TO_SCB_CLK_1X1 |\
55 HRCWL_CSB_TO_CLKIN_4X1 |\
56 HRCWL_VCO_1X2 |\
57 HRCWL_CE_PLL_VCO_DIV_4 |\
58 HRCWL_CE_PLL_DIV_1X1 |\
59 HRCWL_CE_TO_PLL_1X6 |\
60 HRCWL_CORE_TO_CSB_2X1)
61
62#ifdef CONFIG_PCISLAVE
63#define CFG_HRCW_HIGH (\
64 HRCWH_PCI_AGENT |\
65 HRCWH_PCI1_ARBITER_DISABLE |\
66 HRCWH_PCICKDRV_DISABLE |\
67 HRCWH_CORE_ENABLE |\
68 HRCWH_FROM_0XFFF00100 |\
69 HRCWH_BOOTSEQ_DISABLE |\
70 HRCWH_SW_WATCHDOG_DISABLE |\
71 HRCWH_ROM_LOC_LOCAL_16BIT)
72#else
73#define CFG_HRCW_HIGH (\
74 HRCWH_PCI_HOST |\
75 HRCWH_PCI1_ARBITER_ENABLE |\
76 HRCWH_PCICKDRV_ENABLE |\
77 HRCWH_CORE_ENABLE |\
78 HRCWH_FROM_0X00000100 |\
79 HRCWH_BOOTSEQ_DISABLE |\
80 HRCWH_SW_WATCHDOG_DISABLE |\
81 HRCWH_ROM_LOC_LOCAL_16BIT)
82#endif
83
84/*
85 * System IO Config
86 */
87#define CFG_SICRH 0x00000000
88#define CFG_SICRL 0x40000000
89
90#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
91
92/*
93 * IMMR new address
94 */
95#define CFG_IMMRBAR 0xE0000000
96
97/*
98 * DDR Setup
99 */
100#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
101#define CFG_SDRAM_BASE CFG_DDR_BASE
102#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
103
104#undef CONFIG_DDR_ECC /* only for ECC DDR module */
105#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
106
107#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
108#if defined(CONFIG_SPD_EEPROM)
109/*
110 * Determine DDR configuration from I2C interface.
111 */
112#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
113#else
114/*
115 * Manually set up DDR parameters
116 */
117#define CFG_DDR_SIZE 256 /* MB */
118#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
119#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
120#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */
121#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
122#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
123#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */
124#endif
125
126/*
127 * Memory test
128 */
129#undef CFG_DRAM_TEST /* memory test, takes time */
130#define CFG_MEMTEST_START 0x00000000 /* memtest region */
131#define CFG_MEMTEST_END 0x00100000
132
133/*
134 * The reserved memory
135 */
136
137#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
138
139#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
140#define CFG_RAMBOOT
141#else
142#undef CFG_RAMBOOT
143#endif
144
145#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
146#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
147
148/*
149 * Initial RAM Base Address Setup
150 */
151#define CFG_INIT_RAM_LOCK 1
152#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
153#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
154#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
155#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
156
157/*
158 * Local Bus Configuration & Clock Setup
159 */
160#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
161#define CFG_LBC_LBCR 0x00000000
162
163/*
164 * FLASH on the Local Bus
165 */
166#define CFG_FLASH_CFI /* use the Common Flash Interface */
167#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
168#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
169#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
170
171#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
172#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
173
174#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
175 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
176 BR_V) /* valid */
177#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
178
179#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
180#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
181
182#undef CFG_FLASH_CHECKSUM
183
184/*
185 * BCSR on the Local Bus
186 */
187#define CFG_BCSR 0xF8000000
188#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
189#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
190
191#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
192#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
193
194/*
195 * SDRAM on the Local Bus
196 */
197#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
198#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
199
200#define CFG_LB_SDRAM /* if board has SRDAM on local bus */
201
202#ifdef CFG_LB_SDRAM
203#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
204#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
205
206/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
207/*
208 * Base Register 2 and Option Register 2 configure SDRAM.
209 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
210 *
211 * For BR2, need:
212 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
213 * port size = 32-bits = BR2[19:20] = 11
214 * no parity checking = BR2[21:22] = 00
215 * SDRAM for MSEL = BR2[24:26] = 011
216 * Valid = BR[31] = 1
217 *
218 * 0 4 8 12 16 20 24 28
219 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
220 *
221 * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
222 * the top 17 bits of BR2.
223 */
224
225#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
226
227/*
228 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
229 *
230 * For OR2, need:
231 * 64MB mask for AM, OR2[0:7] = 1111 1100
232 * XAM, OR2[17:18] = 11
233 * 9 columns OR2[19-21] = 010
234 * 13 rows OR2[23-25] = 100
235 * EAD set for extra time OR[31] = 1
236 *
237 * 0 4 8 12 16 20 24 28
238 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
239 */
240
241#define CFG_OR2_PRELIM 0xfc006901
242
243#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
244#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
245
246/*
247 * LSDMR masks
248 */
249#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
250#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
251#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
252#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
253#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
254#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
255#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
256#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
257
258#define CFG_LBC_LSDMR_COMMON 0x0063b723
259
260/*
261 * SDRAM Controller configuration sequence.
262 */
263#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
264 | CFG_LBC_LSDMR_OP_PCHALL)
265#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
266 | CFG_LBC_LSDMR_OP_ARFRSH)
267#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
268 | CFG_LBC_LSDMR_OP_ARFRSH)
269#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
270 | CFG_LBC_LSDMR_OP_MRW)
271#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
272 | CFG_LBC_LSDMR_OP_NORMAL)
273
274#endif
275
276/*
277 * Windows to access PIB via local bus
278 */
279#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
280#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
281
282/*
283 * CS4 on Local Bus, to PIB
284 */
285#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
286#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
287
288/*
289 * CS5 on Local Bus, to PIB
290 */
291#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
292#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
293
294/*
295 * Serial Port
296 */
297#define CONFIG_CONS_INDEX 1
298#undef CONFIG_SERIAL_SOFTWARE_FIFO
299#define CFG_NS16550
300#define CFG_NS16550_SERIAL
301#define CFG_NS16550_REG_SIZE 1
302#define CFG_NS16550_CLK get_bus_freq(0)
303
304#define CFG_BAUDRATE_TABLE \
305 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
306
307#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500)
308#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600)
309
310/* Use the HUSH parser */
311#define CFG_HUSH_PARSER
312#ifdef CFG_HUSH_PARSER
313#define CFG_PROMPT_HUSH_PS2 "> "
314#endif
315
316/* I2C */
317#define CONFIG_HARD_I2C /* I2C with hardware support */
318#undef CONFIG_SOFT_I2C /* I2C bit-banged */
319#define CFG_I2C_SPEED 0x3F /* I2C speed and slave address */
320#define CFG_I2C_SLAVE 0x7F
321#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */
322#define CFG_I2C_OFFSET 0x3000
323#define CFG_I2C2_OFFSET 0x3100
324
325/*
326 * Config on-board RTC
327 */
328#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
329#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
330
331/*
332 * General PCI
333 * Addresses are mapped 1-1.
334 */
335#define CFG_PCI_MEM_BASE 0x80000000
336#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
337#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
338#define CFG_PCI_MMIO_BASE 0x90000000
339#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
340#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
341#define CFG_PCI_IO_BASE 0xE0300000
342#define CFG_PCI_IO_PHYS 0xE0300000
343#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
344
345#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
346#define CFG_PCI_SLV_MEM_BUS 0x00000000
347#define CFG_PCI_SLV_MEM_SIZE 0x80000000
348
349
350#ifdef CONFIG_PCI
351
352#define CONFIG_NET_MULTI
353#define CONFIG_PCI_PNP /* do pci plug-and-play */
354
355#undef CONFIG_EEPRO100
356#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
357#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
358
359#endif /* CONFIG_PCI */
360
361
362#ifndef CONFIG_NET_MULTI
363#define CONFIG_NET_MULTI 1
364#endif
365
366/*
Dave Liu7737d5c2006-11-03 12:11:15 -0600[diff] [blame]367 * QE UEC ethernet configuration
368 */
369#define CONFIG_UEC_ETH
370#define CONFIG_ETHPRIME "Freescale GETH"
371#define CONFIG_PHY_MODE_NEED_CHANGE
372
373#define CONFIG_UEC_ETH1 /* GETH1 */
374
375#ifdef CONFIG_UEC_ETH1
376#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
377#define CFG_UEC1_RX_CLK QE_CLK_NONE
378#define CFG_UEC1_TX_CLK QE_CLK9
379#define CFG_UEC1_ETH_TYPE GIGA_ETH
380#define CFG_UEC1_PHY_ADDR 0
381#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
382#endif
383
384#define CONFIG_UEC_ETH2 /* GETH2 */
385
386#ifdef CONFIG_UEC_ETH2
387#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
388#define CFG_UEC2_RX_CLK QE_CLK_NONE
389#define CFG_UEC2_TX_CLK QE_CLK4
390#define CFG_UEC2_ETH_TYPE GIGA_ETH
391#define CFG_UEC2_PHY_ADDR 1
392#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
393#endif
394
395/*
Dave Liu5f820432006-11-03 19:33:44 -0600[diff] [blame]396 * Environment
397 */
398
399#ifndef CFG_RAMBOOT
400 #define CFG_ENV_IS_IN_FLASH 1
401 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
402 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
403 #define CFG_ENV_SIZE 0x2000
404#else
405 #define CFG_NO_FLASH 1 /* Flash is not usable now */
406 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
407 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
408 #define CFG_ENV_SIZE 0x2000
409#endif
410
411#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
412#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
413
414#if defined(CFG_RAMBOOT)
415#if defined(CONFIG_PCI)
416#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
417 | CFG_CMD_PING \
418 | CFG_CMD_ASKENV \
419 | CFG_CMD_PCI \
420 | CFG_CMD_I2C) \
421 & \
422 ~(CFG_CMD_ENV \
423 | CFG_CMD_LOADS))
424#else
425#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
426 | CFG_CMD_PING \
427 | CFG_CMD_ASKENV \
428 | CFG_CMD_I2C) \
429 & \
430 ~(CFG_CMD_ENV \
431 | CFG_CMD_LOADS))
432#endif
433#else
434#if defined(CONFIG_PCI)
435#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
436 | CFG_CMD_PCI \
437 | CFG_CMD_PING \
438 | CFG_CMD_ASKENV \
439 | CFG_CMD_I2C)
440#else
441#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
442 | CFG_CMD_PING \
443 | CFG_CMD_ASKENV \
444 | CFG_CMD_I2C )
445#endif
446#endif
447
448#include <cmd_confdefs.h>
449
450#undef CONFIG_WATCHDOG /* watchdog disabled */
451
452/*
453 * Miscellaneous configurable options
454 */
455#define CFG_LONGHELP /* undef to save memory */
456#define CFG_LOAD_ADDR 0x2000000 /* default load address */
457#define CFG_PROMPT "=> " /* Monitor Command Prompt */
458
459#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
460 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
461#else
462 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
463#endif
464
465#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
466#define CFG_MAXARGS 16 /* max number of command args */
467#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
468#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
469
470/*
471 * For booting Linux, the board info and command line data
472 * have to be in the first 8 MB of memory, since this is
473 * the maximum mapped by the Linux kernel during initialization.
474 */
475#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
476
477/*
478 * Core HID Setup
479 */
480#define CFG_HID0_INIT 0x000000000
481#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
482#define CFG_HID2 HID2_HBE
483
484/*
485 * Cache Config
486 */
487#define CFG_DCACHE_SIZE 32768
488#define CFG_CACHELINE_SIZE 32
489#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
490#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
491#endif
492
493/*
494 * MMU Setup
495 */
496
497/* DDR: cache cacheable */
498#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
499#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
500#define CFG_DBAT0L CFG_IBAT0L
501#define CFG_DBAT0U CFG_IBAT0U
502
503/* IMMRBAR & PCI IO: cache-inhibit and guarded */
504#define CFG_IBAT1L (CFG_IMMRBAR | BATL_PP_10 | \
505 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
506#define CFG_IBAT1U (CFG_IMMRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
507#define CFG_DBAT1L CFG_IBAT1L
508#define CFG_DBAT1U CFG_IBAT1U
509
510/* BCSR: cache-inhibit and guarded */
511#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \
512 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
513#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
514#define CFG_DBAT2L CFG_IBAT2L
515#define CFG_DBAT2U CFG_IBAT2U
516
517/* FLASH: icache cacheable, but dcache-inhibit and guarded */
518#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
519#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
520#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \
521 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
522#define CFG_DBAT3U CFG_IBAT3U
523
524/* Local bus SDRAM: cacheable */
525#define CFG_IBAT4L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
526#define CFG_IBAT4U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
527#define CFG_DBAT4L CFG_IBAT4L
528#define CFG_DBAT4U CFG_IBAT4U
529
530/* Stack in dcache: cacheable, no memory coherence */
531#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
532#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
533#define CFG_DBAT5L CFG_IBAT5L
534#define CFG_DBAT5U CFG_IBAT5U
535
536#ifdef CONFIG_PCI
537/* PCI MEM space: cacheable */
538#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
539#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
540#define CFG_DBAT6L CFG_IBAT6L
541#define CFG_DBAT6U CFG_IBAT6U
542/* PCI MMIO space: cache-inhibit and guarded */
543#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
544 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
545#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
546#define CFG_DBAT7L CFG_IBAT7L
547#define CFG_DBAT7U CFG_IBAT7U
548#else
549#define CFG_IBAT6L (0)
550#define CFG_IBAT6U (0)
551#define CFG_IBAT7L (0)
552#define CFG_IBAT7U (0)
553#define CFG_DBAT6L CFG_IBAT6L
554#define CFG_DBAT6U CFG_IBAT6U
555#define CFG_DBAT7L CFG_IBAT7L
556#define CFG_DBAT7U CFG_IBAT7U
557#endif
558
559/*
560 * Internal Definitions
561 *
562 * Boot Flags
563 */
564#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
565#define BOOTFLAG_WARM 0x02 /* Software reboot */
566
567#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
568#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
569#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
570#endif
571
572/*
573 * Environment Configuration
574 */
575
576#define CONFIG_ENV_OVERWRITE
577
578#if defined(CONFIG_UEC_ETH)
579#define CONFIG_ETHADDR 00:04:9f:ef:01:01
580#define CONFIG_HAS_ETH1
581#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
582#endif
583
584#define CONFIG_BAUDRATE 115200
585
586#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
587
588#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
589#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
590
591#define CONFIG_EXTRA_ENV_SETTINGS \
592 "netdev=eth0\0" \
593 "consoledev=ttyS0\0" \
594 "ramdiskaddr=400000\0" \
595 "ramdiskfile=ramfs.83xx\0" \
596
597#define CONFIG_NFSBOOTCOMMAND \
598 "setenv bootargs root=/dev/nfs rw " \
599 "nfsroot=$serverip:$rootpath " \
600 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
601 "console=$consoledev,$baudrate $othbootargs;" \
602 "tftp $loadaddr $bootfile;" \
603 "bootm $loadaddr"
604
605#define CONFIG_RAMBOOTCOMMAND \
606 "setenv bootargs root=/dev/ram rw " \
607 "console=$consoledev,$baudrate $othbootargs;" \
608 "tftp $ramdiskaddr $ramdiskfile;" \
609 "tftp $loadaddr $bootfile;" \
610 "bootm $loadaddr $ramdiskaddr"
611
612#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
613
614#endif /* __CONFIG_H */