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Hannes Petermaier3c5fabd2014-03-06 14:39:06 +01001/*
Hannes Schmelzere880a5e2018-01-09 19:01:32 +01002 * Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at>
3 * B&R Industrial Automation GmbH - http://www.br-automation.com
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +01004 *
5 * minimal framebuffer driver for TI's AM335x SoC to be compatible with
6 * Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
7 *
Martin Pietryka7d045172016-04-27 21:39:15 +02008 * - supporting 16/24/32bit RGB/TFT raster Mode (not using palette)
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +01009 * - sets up LCD controller as in 'am335x_lcdpanel' struct given
10 * - starts output DMA from gd->fb_base buffer
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14#include <common.h>
Hannes Schmelzer8a094f52018-01-09 19:01:34 +010015#include <asm/io.h>
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +010016#include <asm/arch/hardware.h>
Hannes Schmelzer8a094f52018-01-09 19:01:34 +010017#include <asm/arch/omap.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/sys_proto.h>
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +010020#include <lcd.h>
21#include "am335x-fb.h"
22
23#if !defined(LCD_CNTL_BASE)
24#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
25#endif
26
Hannes Schmelzer8a094f52018-01-09 19:01:34 +010027#define LCDC_FMAX 200000000
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +010028
29/* LCD Control Register */
30#define LCD_CLK_DIVISOR(x) ((x) << 8)
31#define LCD_RASTER_MODE 0x01
32/* LCD Clock Enable Register */
33#define LCD_CORECLKEN (0x01 << 0)
34#define LCD_LIDDCLKEN (0x01 << 1)
35#define LCD_DMACLKEN (0x01 << 2)
36/* LCD DMA Control Register */
37#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
38#define LCD_DMA_BURST_1 0x0
39#define LCD_DMA_BURST_2 0x1
40#define LCD_DMA_BURST_4 0x2
41#define LCD_DMA_BURST_8 0x3
42#define LCD_DMA_BURST_16 0x4
43/* LCD Timing_0 Register */
44#define LCD_HBPLSB(x) ((((x)-1) & 0xFF) << 24)
45#define LCD_HFPLSB(x) ((((x)-1) & 0xFF) << 16)
46#define LCD_HSWLSB(x) ((((x)-1) & 0x3F) << 10)
47#define LCD_HORLSB(x) (((((x) >> 4)-1) & 0x3F) << 4)
48#define LCD_HORMSB(x) (((((x) >> 4)-1) & 0x40) >> 4)
49/* LCD Timing_1 Register */
50#define LCD_VBP(x) ((x) << 24)
51#define LCD_VFP(x) ((x) << 16)
52#define LCD_VSW(x) (((x)-1) << 10)
53#define LCD_VERLSB(x) (((x)-1) & 0x3FF)
54/* LCD Timing_2 Register */
55#define LCD_HSWMSB(x) ((((x)-1) & 0x3C0) << 21)
56#define LCD_VERMSB(x) ((((x)-1) & 0x400) << 16)
57#define LCD_HBPMSB(x) ((((x)-1) & 0x300) >> 4)
58#define LCD_HFPMSB(x) ((((x)-1) & 0x300) >> 8)
59#define LCD_INVMASK(x) ((x) & 0x3F00000)
60/* LCD Raster Ctrl Register */
61#define LCD_TFT_24BPP_MODE (1 << 25)
62#define LCD_TFT_24BPP_UNPACK (1 << 26)
Martin Pietrykaac5c61b2016-04-25 21:25:07 +020063#define LCD_PALMODE_RAWDATA (0x02 << 20)
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +010064#define LCD_TFT_MODE (0x01 << 7)
65#define LCD_RASTER_ENABLE (0x01 << 0)
66
67
68/* Macro definitions */
69#define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3)
70
71struct am335x_lcdhw {
72 unsigned int pid; /* 0x00 */
73 unsigned int ctrl; /* 0x04 */
74 unsigned int gap0; /* 0x08 */
75 unsigned int lidd_ctrl; /* 0x0C */
76 unsigned int lidd_cs0_conf; /* 0x10 */
77 unsigned int lidd_cs0_addr; /* 0x14 */
78 unsigned int lidd_cs0_data; /* 0x18 */
79 unsigned int lidd_cs1_conf; /* 0x1C */
80 unsigned int lidd_cs1_addr; /* 0x20 */
81 unsigned int lidd_cs1_data; /* 0x24 */
82 unsigned int raster_ctrl; /* 0x28 */
83 unsigned int raster_timing0; /* 0x2C */
84 unsigned int raster_timing1; /* 0x30 */
85 unsigned int raster_timing2; /* 0x34 */
86 unsigned int raster_subpanel; /* 0x38 */
87 unsigned int raster_subpanel2; /* 0x3C */
88 unsigned int lcddma_ctrl; /* 0x40 */
89 unsigned int lcddma_fb0_base; /* 0x44 */
90 unsigned int lcddma_fb0_ceiling; /* 0x48 */
91 unsigned int lcddma_fb1_base; /* 0x4C */
92 unsigned int lcddma_fb1_ceiling; /* 0x50 */
93 unsigned int sysconfig; /* 0x54 */
94 unsigned int irqstatus_raw; /* 0x58 */
95 unsigned int irqstatus; /* 0x5C */
96 unsigned int irqenable_set; /* 0x60 */
97 unsigned int irqenable_clear; /* 0x64 */
98 unsigned int gap1; /* 0x68 */
99 unsigned int clkc_enable; /* 0x6C */
100 unsigned int clkc_reset; /* 0x70 */
101};
102
103static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
Hannes Schmelzer8a094f52018-01-09 19:01:34 +0100104
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100105DECLARE_GLOBAL_DATA_PTR;
106
107int lcd_get_size(int *line_length)
108{
109 *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
110 return *line_length * panel_info.vl_row + 0x20;
111}
112
113int am335xfb_init(struct am335x_lcdpanel *panel)
114{
Martin Pietryka7d045172016-04-27 21:39:15 +0200115 u32 raster_ctrl = 0;
116
Hannes Schmelzer8a094f52018-01-09 19:01:34 +0100117 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
118 struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
119 unsigned int m, n, d, best_d = 2;
120 int err = 0, err_r = 0;
121
Hannes Schmelzer0d8a7d62018-01-09 19:01:33 +0100122 if (gd->fb_base == 0) {
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100123 printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
124 return -1;
125 }
Hannes Schmelzer0d8a7d62018-01-09 19:01:33 +0100126 if (panel == NULL) {
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100127 printf("ERROR: missing ptr to am335x_lcdpanel!\n");
128 return -1;
129 }
130
Martin Pietryka7d045172016-04-27 21:39:15 +0200131 /* We can already set the bits for the raster_ctrl in this check */
132 switch (panel->bpp) {
133 case 16:
134 break;
135 case 32:
136 raster_ctrl |= LCD_TFT_24BPP_UNPACK;
137 /* fallthrough */
138 case 24:
139 raster_ctrl |= LCD_TFT_24BPP_MODE;
140 break;
141 default:
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900142 pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp);
Martin Pietryka7d045172016-04-27 21:39:15 +0200143 return -1;
144 }
145
Hannes Schmelzer8a094f52018-01-09 19:01:34 +0100146 /* check given clock-frequency */
147 if (panel->pxl_clk > (LCDC_FMAX / 2)) {
148 pr_err("am335x-fb: requested pxl-clk: %d not supported!\n",
149 panel->pxl_clk);
150 return -1;
151 }
152
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100153 debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
154 panel->hactive, panel->vactive, panel->bpp,
155 panel->hfp, panel->hbp, panel->hsw);
Hannes Schmelzer8a094f52018-01-09 19:01:34 +0100156 debug("vfp=%d,vbp=%d,vsw=%d / clk=%d)\n",
157 panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk);
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100158 debug("using frambuffer at 0x%08x with size %d.\n",
159 (unsigned int)gd->fb_base, FBSIZE(panel));
160
Hannes Schmelzer8a094f52018-01-09 19:01:34 +0100161 /* setup display pll for requested clock frequency */
162 err = panel->pxl_clk;
163 err_r = err;
164
165 for (d = 2; d < 255; d++) {
166 for (m = 2; m < 2047; m++) {
167 if ((V_OSCK * m) < (panel->pxl_clk * d))
168 continue;
169 n = (V_OSCK * m) / (panel->pxl_clk * d);
170 if (n > 127)
171 break;
172 if (((V_OSCK * m) / n) > LCDC_FMAX)
173 break;
174
175 err = abs((V_OSCK * m) / n / d - panel->pxl_clk);
176 if (err < err_r) {
177 err_r = err;
178 dpll_disp.m = m;
179 dpll_disp.n = n;
180 best_d = d;
181 }
182 }
183 }
184 debug("%s: PLL: best error %d Hz (M %d, N %d, DISP %d)\n",
185 __func__, err_r, dpll_disp.m, dpll_disp.n, best_d);
186 do_setup_dpll(&dpll_disp_regs, &dpll_disp);
187
188 /* clock source for LCDC from dispPLL M2 */
189 writel(0x0, &cmdpll->clklcdcpixelclk);
190
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100191 /* palette default entry */
192 memset((void *)gd->fb_base, 0, 0x20);
193 *(unsigned int *)gd->fb_base = 0x4000;
Martin Pietryka3d47b2d2016-04-27 21:39:16 +0200194 /* point fb behind palette */
195 gd->fb_base += 0x20;
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100196
Hannes Petermaier3b4e16e2015-02-03 13:22:23 +0100197 /* turn ON display through powercontrol function if accessible */
Hannes Schmelzer0d8a7d62018-01-09 19:01:33 +0100198 if (panel->panel_power_ctrl != NULL)
Hannes Petermaier3b4e16e2015-02-03 13:22:23 +0100199 panel->panel_power_ctrl(1);
200
201 debug("am335x-fb: wait for stable power ...\n");
202 mdelay(panel->pup_delay);
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100203 lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
204 lcdhw->raster_ctrl = 0;
Hannes Schmelzer8a094f52018-01-09 19:01:34 +0100205 lcdhw->ctrl = LCD_CLK_DIVISOR(best_d) | LCD_RASTER_MODE;
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100206 lcdhw->lcddma_fb0_base = gd->fb_base;
Martin Pietryka3d47b2d2016-04-27 21:39:16 +0200207 lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100208 lcdhw->lcddma_fb1_base = gd->fb_base;
Martin Pietryka3d47b2d2016-04-27 21:39:16 +0200209 lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel);
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100210 lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
211
212 lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) |
213 LCD_HORMSB(panel->hactive) |
214 LCD_HFPLSB(panel->hfp) |
215 LCD_HBPLSB(panel->hbp) |
216 LCD_HSWLSB(panel->hsw);
217 lcdhw->raster_timing1 = LCD_VBP(panel->vbp) |
218 LCD_VFP(panel->vfp) |
219 LCD_VSW(panel->vsw) |
220 LCD_VERLSB(panel->vactive);
221 lcdhw->raster_timing2 = LCD_HSWMSB(panel->hsw) |
222 LCD_VERMSB(panel->vactive) |
223 LCD_INVMASK(panel->pol) |
224 LCD_HBPMSB(panel->hbp) |
225 LCD_HFPMSB(panel->hfp) |
226 0x0000FF00; /* clk cycles for ac-bias */
Martin Pietryka7d045172016-04-27 21:39:15 +0200227 lcdhw->raster_ctrl = raster_ctrl |
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100228 LCD_PALMODE_RAWDATA |
229 LCD_TFT_MODE |
230 LCD_RASTER_ENABLE;
231
Hannes Petermaier3b4e16e2015-02-03 13:22:23 +0100232 debug("am335x-fb: waiting picture to be stable.\n.");
233 mdelay(panel->pon_delay);
Hannes Petermaier3c5fabd2014-03-06 14:39:06 +0100234
235 return 0;
236}