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Dario Binacchiea45b8f2020-12-30 00:06:35 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * TI clock utilities
4 *
5 * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
6 */
7
8#include <common.h>
Dario Binacchib1aef032021-05-01 17:05:22 +02009#include <dm.h>
Simon Glass401d1c42020-10-30 21:38:53 -060010#include <fdtdec.h>
Dario Binacchib1aef032021-05-01 17:05:22 +020011#include <regmap.h>
Dario Binacchiea45b8f2020-12-30 00:06:35 +010012#include <asm/io.h>
Dario Binacchib1aef032021-05-01 17:05:22 +020013#include <dm/device_compat.h>
Dario Binacchiea45b8f2020-12-30 00:06:35 +010014#include "clk.h"
15
Dario Binacchib1aef032021-05-01 17:05:22 +020016#define CLK_MAX_MEMMAPS 10
17
18struct clk_iomap {
19 struct regmap *regmap;
20 ofnode node;
21};
22
23static unsigned int clk_memmaps_num;
24static struct clk_iomap clk_memmaps[CLK_MAX_MEMMAPS];
25
Dario Binacchi2dd2f3ea2021-05-01 17:05:23 +020026static void clk_ti_rmw(u32 val, u32 mask, struct clk_ti_reg *reg)
Dario Binacchiea45b8f2020-12-30 00:06:35 +010027{
28 u32 v;
29
Dario Binacchi2dd2f3ea2021-05-01 17:05:23 +020030 v = clk_ti_readl(reg);
Dario Binacchiea45b8f2020-12-30 00:06:35 +010031 v &= ~mask;
32 v |= val;
Dario Binacchi2dd2f3ea2021-05-01 17:05:23 +020033 clk_ti_writel(v, reg);
Dario Binacchiea45b8f2020-12-30 00:06:35 +010034}
35
Dario Binacchi2dd2f3ea2021-05-01 17:05:23 +020036void clk_ti_latch(struct clk_ti_reg *reg, s8 shift)
Dario Binacchiea45b8f2020-12-30 00:06:35 +010037{
38 u32 latch;
39
40 if (shift < 0)
41 return;
42
43 latch = 1 << shift;
44
45 clk_ti_rmw(latch, latch, reg);
46 clk_ti_rmw(0, latch, reg);
Dario Binacchi2dd2f3ea2021-05-01 17:05:23 +020047 clk_ti_readl(reg); /* OCP barrier */
Dario Binacchiea45b8f2020-12-30 00:06:35 +010048}
Dario Binacchib1aef032021-05-01 17:05:22 +020049
50void clk_ti_writel(u32 val, struct clk_ti_reg *reg)
51{
52 struct clk_iomap *io = &clk_memmaps[reg->index];
53
54 regmap_write(io->regmap, reg->offset, val);
55}
56
57u32 clk_ti_readl(struct clk_ti_reg *reg)
58{
59 struct clk_iomap *io = &clk_memmaps[reg->index];
60 u32 val;
61
62 regmap_read(io->regmap, reg->offset, &val);
63 return val;
64}
65
66static ofnode clk_ti_get_regmap_node(struct udevice *dev)
67{
68 ofnode node = dev_ofnode(dev), parent;
69
70 if (!ofnode_valid(node))
71 return ofnode_null();
72
73 parent = ofnode_get_parent(node);
74 if (strcmp(ofnode_get_name(parent), "clocks"))
75 return ofnode_null();
76
77 return ofnode_get_parent(parent);
78}
79
80int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg *reg)
81{
82 ofnode node;
83 int i, ret;
84 u32 val;
85
86 ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", index, &val);
87 if (ret) {
88 dev_err(dev, "%s must have reg[%d]\n", ofnode_get_name(node),
89 index);
90 return ret;
91 }
92
93 /* parent = ofnode_get_parent(parent); */
94 node = clk_ti_get_regmap_node(dev);
95 if (!ofnode_valid(node)) {
96 dev_err(dev, "failed to get regmap node\n");
97 return -EFAULT;
98 }
99
100 for (i = 0; i < clk_memmaps_num; i++) {
101 if (ofnode_equal(clk_memmaps[i].node, node))
102 break;
103 }
104
105 if (i == clk_memmaps_num) {
106 if (i == CLK_MAX_MEMMAPS)
107 return -ENOMEM;
108
109 ret = regmap_init_mem(node, &clk_memmaps[i].regmap);
110 if (ret)
111 return ret;
112
113 clk_memmaps[i].node = node;
114 clk_memmaps_num++;
115 }
116
117 reg->index = i;
118 reg->offset = val;
119 return 0;
120}