Michael Walle | e057760 | 2020-11-18 17:46:01 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * LS1028A TF-A calling support |
| 4 | * |
| 5 | * Copyright (c) 2020 Michael Walle <michael@walle.cc> |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 9 | #include <asm/global_data.h> |
Michael Walle | e057760 | 2020-11-18 17:46:01 +0100 | [diff] [blame] | 10 | #include <asm/io.h> |
| 11 | #include <atf_common.h> |
| 12 | #include <spl.h> |
| 13 | |
| 14 | DECLARE_GLOBAL_DATA_PTR; |
| 15 | |
| 16 | struct region_info { |
| 17 | u64 addr; |
| 18 | u64 size; |
| 19 | }; |
| 20 | |
| 21 | struct dram_regions_info { |
| 22 | u64 num_dram_regions; |
| 23 | u64 total_dram_size; |
| 24 | struct region_info region[CONFIG_NR_DRAM_BANKS]; |
| 25 | }; |
| 26 | |
| 27 | struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, |
| 28 | uintptr_t bl33_entry, |
| 29 | uintptr_t fdt_addr) |
| 30 | { |
| 31 | static struct dram_regions_info dram_regions_info = { 0 }; |
| 32 | struct bl_params *bl_params; |
| 33 | struct bl_params_node *node; |
| 34 | void *dcfg_ccsr = (void *)DCFG_BASE; |
| 35 | int i; |
| 36 | |
| 37 | dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS; |
| 38 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
| 39 | dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start; |
| 40 | dram_regions_info.region[i].size = gd->bd->bi_dram[i].size; |
| 41 | dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size; |
| 42 | } |
| 43 | |
| 44 | bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry, |
| 45 | fdt_addr); |
| 46 | |
| 47 | for_each_bl_params_node(bl_params, node) { |
| 48 | if (node->image_id == ATF_BL31_IMAGE_ID) { |
| 49 | node->ep_info->args.arg3 = (uintptr_t)&dram_regions_info; |
| 50 | node->ep_info->args.arg4 = in_le32(dcfg_ccsr + DCFG_PORSR1); |
| 51 | } |
| 52 | } |
| 53 | |
| 54 | return bl_params; |
| 55 | } |