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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05302/*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05305 */
6
7#include <common.h>
York Sun0b665132013-10-22 12:39:02 -07008#include <fsl_ifc.h>
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05309
Pankit Garg9bd5fe72018-11-05 18:01:33 +000010struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
11 {
12 "cs0",
13#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
14 CONFIG_SYS_CSPR0,
15#ifdef CONFIG_SYS_CSPR0_EXT
16 CONFIG_SYS_CSPR0_EXT,
17#else
18 0,
19#endif
20#ifdef CONFIG_SYS_AMASK0
21 CONFIG_SYS_AMASK0,
22#else
23 0,
24#endif
25 CONFIG_SYS_CSOR0,
26 {
27 CONFIG_SYS_CS0_FTIM0,
28 CONFIG_SYS_CS0_FTIM1,
29 CONFIG_SYS_CS0_FTIM2,
30 CONFIG_SYS_CS0_FTIM3,
31 },
32#ifdef CONFIG_SYS_CSOR0_EXT
33 CONFIG_SYS_CSOR0_EXT,
34#else
35 0,
36#endif
37#ifdef CONFIG_SYS_CSPR0_FINAL
38 CONFIG_SYS_CSPR0_FINAL,
39#else
40 0,
41#endif
42#ifdef CONFIG_SYS_AMASK0_FINAL
43 CONFIG_SYS_AMASK0_FINAL,
44#else
45 0,
46#endif
47#endif
48 },
49
50#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2
51 {
52 "cs1",
53#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
54 CONFIG_SYS_CSPR1,
55#ifdef CONFIG_SYS_CSPR1_EXT
56 CONFIG_SYS_CSPR1_EXT,
57#else
58 0,
59#endif
60#ifdef CONFIG_SYS_AMASK1
61 CONFIG_SYS_AMASK1,
62#else
63 0,
64#endif
65 CONFIG_SYS_CSOR1,
66 {
67 CONFIG_SYS_CS1_FTIM0,
68 CONFIG_SYS_CS1_FTIM1,
69 CONFIG_SYS_CS1_FTIM2,
70 CONFIG_SYS_CS1_FTIM3,
71 },
72#ifdef CONFIG_SYS_CSOR1_EXT
73 CONFIG_SYS_CSOR1_EXT,
74#else
75 0,
76#endif
77#ifdef CONFIG_SYS_CSPR1_FINAL
78 CONFIG_SYS_CSPR1_FINAL,
79#else
80 0,
81#endif
82#ifdef CONFIG_SYS_AMASK1_FINAL
83 CONFIG_SYS_AMASK1_FINAL,
84#else
85 0,
86#endif
87#endif
88 },
89#endif
90
91#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3
92 {
93 "cs2",
94#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
95 CONFIG_SYS_CSPR2,
96#ifdef CONFIG_SYS_CSPR2_EXT
97 CONFIG_SYS_CSPR2_EXT,
98#else
99 0,
100#endif
101#ifdef CONFIG_SYS_AMASK2
102 CONFIG_SYS_AMASK2,
103#else
104 0,
105#endif
106 CONFIG_SYS_CSOR2,
107 {
108 CONFIG_SYS_CS2_FTIM0,
109 CONFIG_SYS_CS2_FTIM1,
110 CONFIG_SYS_CS2_FTIM2,
111 CONFIG_SYS_CS2_FTIM3,
112 },
113#ifdef CONFIG_SYS_CSOR2_EXT
114 CONFIG_SYS_CSOR2_EXT,
115#else
116 0,
117#endif
118#ifdef CONFIG_SYS_CSPR2_FINAL
119 CONFIG_SYS_CSPR2_FINAL,
120#else
121 0,
122#endif
123#ifdef CONFIG_SYS_AMASK2_FINAL
124 CONFIG_SYS_AMASK2_FINAL,
125#else
126 0,
127#endif
128#endif
129 },
130#endif
131
132#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4
133 {
134 "cs3",
135#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
136 CONFIG_SYS_CSPR3,
137#ifdef CONFIG_SYS_CSPR3_EXT
138 CONFIG_SYS_CSPR3_EXT,
139#else
140 0,
141#endif
142#ifdef CONFIG_SYS_AMASK3
143 CONFIG_SYS_AMASK3,
144#else
145 0,
146#endif
147 CONFIG_SYS_CSOR3,
148 {
149 CONFIG_SYS_CS3_FTIM0,
150 CONFIG_SYS_CS3_FTIM1,
151 CONFIG_SYS_CS3_FTIM2,
152 CONFIG_SYS_CS3_FTIM3,
153 },
154#ifdef CONFIG_SYS_CSOR3_EXT
155 CONFIG_SYS_CSOR3_EXT,
156#else
157 0,
158#endif
159#ifdef CONFIG_SYS_CSPR3_FINAL
160 CONFIG_SYS_CSPR3_FINAL,
161#else
162 0,
163#endif
164#ifdef CONFIG_SYS_AMASK3_FINAL
165 CONFIG_SYS_AMASK3_FINAL,
166#else
167 0,
168#endif
169#endif
170 },
171#endif
172
173#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5
174 {
175 "cs4",
176#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
177 CONFIG_SYS_CSPR4,
178#ifdef CONFIG_SYS_CSPR4_EXT
179 CONFIG_SYS_CSPR4_EXT,
180#else
181 0,
182#endif
183#ifdef CONFIG_SYS_AMASK4
184 CONFIG_SYS_AMASK4,
185#else
186 0,
187#endif
188 CONFIG_SYS_CSOR4,
189 {
190 CONFIG_SYS_CS4_FTIM0,
191 CONFIG_SYS_CS4_FTIM1,
192 CONFIG_SYS_CS4_FTIM2,
193 CONFIG_SYS_CS4_FTIM3,
194 },
195#ifdef CONFIG_SYS_CSOR4_EXT
196 CONFIG_SYS_CSOR4_EXT,
197#else
198 0,
199#endif
200#ifdef CONFIG_SYS_CSPR4_FINAL
201 CONFIG_SYS_CSPR4_FINAL,
202#else
203 0,
204#endif
205#ifdef CONFIG_SYS_AMASK4_FINAL
206 CONFIG_SYS_AMASK4_FINAL,
207#else
208 0,
209#endif
210#endif
211 },
212#endif
213
214#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 6
215 {
216 "cs5",
217#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
218 CONFIG_SYS_CSPR5,
219#ifdef CONFIG_SYS_CSPR5_EXT
220 CONFIG_SYS_CSPR5_EXT,
221#else
222 0,
223#endif
224#ifdef CONFIG_SYS_AMASK5
225 CONFIG_SYS_AMASK5,
226#else
227 0,
228#endif
229 CONFIG_SYS_CSOR5,
230 {
231 CONFIG_SYS_CS5_FTIM0,
232 CONFIG_SYS_CS5_FTIM1,
233 CONFIG_SYS_CS5_FTIM2,
234 CONFIG_SYS_CS5_FTIM3,
235 },
236#ifdef CONFIG_SYS_CSOR5_EXT
237 CONFIG_SYS_CSOR5_EXT,
238#else
239 0,
240#endif
241#ifdef CONFIG_SYS_CSPR5_FINAL
242 CONFIG_SYS_CSPR5_FINAL,
243#else
244 0,
245#endif
246#ifdef CONFIG_SYS_AMASK5_FINAL
247 CONFIG_SYS_AMASK5_FINAL,
248#else
249 0,
250#endif
251#endif
252 },
253#endif
254
255#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7
256 {
257 "cs6",
258#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
259 CONFIG_SYS_CSPR6,
260#ifdef CONFIG_SYS_CSPR6_EXT
261 CONFIG_SYS_CSPR6_EXT,
262#else
263 0,
264#endif
265#ifdef CONFIG_SYS_AMASK6
266 CONFIG_SYS_AMASK6,
267#else
268 0,
269#endif
270 CONFIG_SYS_CSOR6,
271 {
272 CONFIG_SYS_CS6_FTIM0,
273 CONFIG_SYS_CS6_FTIM1,
274 CONFIG_SYS_CS6_FTIM2,
275 CONFIG_SYS_CS6_FTIM3,
276 },
277#ifdef CONFIG_SYS_CSOR6_EXT
278 CONFIG_SYS_CSOR6_EXT,
279#else
280 0,
281#endif
282#ifdef CONFIG_SYS_CSPR6_FINAL
283 CONFIG_SYS_CSPR6_FINAL,
284#else
285 0,
286#endif
287#ifdef CONFIG_SYS_AMASK6_FINAL
288 CONFIG_SYS_AMASK6_FINAL,
289#else
290 0,
291#endif
292#endif
293 },
294#endif
295
296#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8
297 {
298 "cs7",
299#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
300 CONFIG_SYS_CSPR7,
301#ifdef CONFIG_SYS_CSPR7_EXT
302 CONFIG_SYS_CSPR7_EXT,
303#else
304 0,
305#endif
306#ifdef CONFIG_SYS_AMASK7
307 CONFIG_SYS_AMASK7,
308#else
309 0,
310#endif
311 CONFIG_SYS_CSOR7,
312#ifdef CONFIG_SYS_CSOR7_EXT
313 CONFIG_SYS_CSOR7_EXT,
314#else
315 0,
316#endif
317 {
318 CONFIG_SYS_CS7_FTIM0,
319 CONFIG_SYS_CS7_FTIM1,
320 CONFIG_SYS_CS7_FTIM2,
321 CONFIG_SYS_CS7_FTIM3,
322 },
323#ifdef CONFIG_SYS_CSPR7_FINAL
324 CONFIG_SYS_CSPR7_FINAL,
325#else
326 0,
327#endif
328#ifdef CONFIG_SYS_AMASK7_FINAL
329 CONFIG_SYS_AMASK7_FINAL,
330#else
331 0,
332#endif
333#endif
334 },
335#endif
336};
337
338__weak void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
339{
340 regs_info->regs = ifc_cfg_default_boot;
341 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
342}
343
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530344void print_ifc_regs(void)
345{
346 int i, j;
347
348 printf("IFC Controller Registers\n");
Mingkai Hu362ee042013-05-16 10:18:13 +0800349 for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530350 printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
Pankit Garg9bd5fe72018-11-05 18:01:33 +0000351 i, get_ifc_cspr(i), i, get_ifc_amask(i),
352 i, get_ifc_csor(i));
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530353 for (j = 0; j < 4; j++)
354 printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j));
355 }
356}
357
358void init_early_memctl_regs(void)
359{
Pankit Garg9bd5fe72018-11-05 18:01:33 +0000360 int i, j;
361 struct ifc_regs *regs;
362 struct ifc_regs_info regs_info = {0};
Dipen Dudhatd7da1482011-04-08 16:04:51 +0530363
Pankit Garg9bd5fe72018-11-05 18:01:33 +0000364 ifc_cfg_boot_info(&regs_info);
365 regs = regs_info.regs;
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530366
Pankit Garg9bd5fe72018-11-05 18:01:33 +0000367 for (i = 0 ; i < regs_info.cs_size; i++) {
368 if (regs[i].pr && (regs[i].pr & CSPR_V)) {
369 /* skip setting cspr/csor_ext in below condition */
370 if (!(CONFIG_IS_ENABLED(A003399_NOR_WORKAROUND) &&
371 i == 0 &&
372 ((regs[0].pr & CSPR_MSEL) == CSPR_MSEL_NOR))) {
373 if (regs[i].pr_ext)
374 set_ifc_cspr_ext(i, regs[i].pr_ext);
375 if (regs[i].or_ext)
376 set_ifc_csor_ext(i, regs[i].or_ext);
377 }
Dipen Dudhatd7da1482011-04-08 16:04:51 +0530378
Pankit Garg9bd5fe72018-11-05 18:01:33 +0000379 for (j = 0; j < ARRAY_SIZE(regs->ftim); j++)
380 set_ifc_ftim(i, j, regs[i].ftim[j]);
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530381
Pankit Garg9bd5fe72018-11-05 18:01:33 +0000382 set_ifc_csor(i, regs[i].or);
383 set_ifc_amask(i, regs[i].amask);
384 set_ifc_cspr(i, regs[i].pr);
385 }
386 }
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530387}
York Sune77224e2014-03-19 13:52:34 -0700388
389void init_final_memctl_regs(void)
390{
Pankit Garg9bd5fe72018-11-05 18:01:33 +0000391 int i;
392 struct ifc_regs *regs;
393 struct ifc_regs_info regs_info;
394
395 ifc_cfg_boot_info(&regs_info);
396 regs = regs_info.regs;
397
398 for (i = 0 ; i < regs_info.cs_size && i < ARRAY_SIZE(regs->ftim); i++) {
399 if (!(regs[i].pr_final & CSPR_V))
400 continue;
401 if (regs[i].pr_final)
402 set_ifc_cspr(i, regs[i].pr_final);
403 if (regs[i].amask_final)
404 set_ifc_amask(i, (i == 1) ? regs[i].amask_final :
405 regs[i].amask);
406 }
York Sune77224e2014-03-19 13:52:34 -0700407}