blob: bbdb76bd574f5c835b40e7180843c0cfd3268d2e [file] [log] [blame]
Rick Chen4fa42672019-08-28 18:46:06 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
5 */
6
7#include <common.h>
8#include <command.h>
9#include <cache.h>
10#include <dm.h>
Simon Glassdb41d652019-12-28 10:45:07 -070011#include <hang.h>
Simon Glass401d1c42020-10-30 21:38:53 -060012#include <asm/global_data.h>
Rick Chen4fa42672019-08-28 18:46:06 +080013#include <asm/io.h>
14#include <dm/ofnode.h>
Simon Glasscd93d622020-05-10 11:40:13 -060015#include <linux/bitops.h>
Rick Chen4fa42672019-08-28 18:46:06 +080016
17struct l2cache {
18 volatile u64 configure;
19 volatile u64 control;
20 volatile u64 hpm0;
21 volatile u64 hpm1;
22 volatile u64 hpm2;
23 volatile u64 hpm3;
24 volatile u64 error_status;
25 volatile u64 ecc_error;
26 volatile u64 cctl_command0;
27 volatile u64 cctl_access_line0;
28 volatile u64 cctl_command1;
29 volatile u64 cctl_access_line1;
30 volatile u64 cctl_command2;
31 volatile u64 cctl_access_line2;
32 volatile u64 cctl_command3;
33 volatile u64 cctl_access_line4;
34 volatile u64 cctl_status;
35};
36
37/* Control Register */
38#define L2_ENABLE 0x1
39/* prefetch */
40#define IPREPETCH_OFF 3
41#define DPREPETCH_OFF 5
42#define IPREPETCH_MSK (3 << IPREPETCH_OFF)
43#define DPREPETCH_MSK (3 << DPREPETCH_OFF)
44/* tag ram */
45#define TRAMOCTL_OFF 8
46#define TRAMICTL_OFF 10
47#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
48#define TRAMICTL_MSK BIT(TRAMICTL_OFF)
49/* data ram */
50#define DRAMOCTL_OFF 11
51#define DRAMICTL_OFF 13
52#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
53#define DRAMICTL_MSK BIT(DRAMICTL_OFF)
54
55/* CCTL Command Register */
56#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
57#define L2_WBINVAL_ALL 0x12
58
59/* CCTL Status Register */
60#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
61#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
62#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
63#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
64
65DECLARE_GLOBAL_DATA_PTR;
66
67struct v5l2_plat {
68 struct l2cache *regs;
69 u32 iprefetch;
70 u32 dprefetch;
Wolfgang Denk0cf207e2021-09-27 17:42:39 +020071 u32 tram_ctl[2];
72 u32 dram_ctl[2];
Rick Chen4fa42672019-08-28 18:46:06 +080073};
74
75static int v5l2_enable(struct udevice *dev)
76{
Simon Glassc69cda22020-12-03 16:55:20 -070077 struct v5l2_plat *plat = dev_get_plat(dev);
Rick Chen4fa42672019-08-28 18:46:06 +080078 volatile struct l2cache *regs = plat->regs;
79
80 if (regs)
81 setbits_le32(&regs->control, L2_ENABLE);
82
83 return 0;
84}
85
86static int v5l2_disable(struct udevice *dev)
87{
Simon Glassc69cda22020-12-03 16:55:20 -070088 struct v5l2_plat *plat = dev_get_plat(dev);
Rick Chen4fa42672019-08-28 18:46:06 +080089 volatile struct l2cache *regs = plat->regs;
90 u8 hart = gd->arch.boot_hart;
91 void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
92
93 if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
94 writel(L2_WBINVAL_ALL, cctlcmd);
95
96 while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) {
97 if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
98 printf("L2 flush illegal! hanging...");
99 hang();
100 }
101 }
102 clrbits_le32(&regs->control, L2_ENABLE);
103 }
104
105 return 0;
106}
107
Simon Glassd1998a92020-12-03 16:55:21 -0700108static int v5l2_of_to_plat(struct udevice *dev)
Rick Chen4fa42672019-08-28 18:46:06 +0800109{
Simon Glassc69cda22020-12-03 16:55:20 -0700110 struct v5l2_plat *plat = dev_get_plat(dev);
Rick Chen4fa42672019-08-28 18:46:06 +0800111 struct l2cache *regs;
112
113 regs = (struct l2cache *)dev_read_addr(dev);
114 plat->regs = regs;
115
116 plat->iprefetch = -EINVAL;
117 plat->dprefetch = -EINVAL;
118 plat->tram_ctl[0] = -EINVAL;
119 plat->dram_ctl[0] = -EINVAL;
120
121 /* Instruction and data fetch prefetch depth */
122 dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
123 dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
124
125 /* Set tag RAM and data RAM setup and output cycle */
126 dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
127 dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
128
129 return 0;
130}
131
132static int v5l2_probe(struct udevice *dev)
133{
Simon Glassc69cda22020-12-03 16:55:20 -0700134 struct v5l2_plat *plat = dev_get_plat(dev);
Rick Chen4fa42672019-08-28 18:46:06 +0800135 struct l2cache *regs = plat->regs;
136 u32 ctl_val;
137
138 ctl_val = readl(&regs->control);
139
140 if (!(ctl_val & L2_ENABLE))
141 ctl_val |= L2_ENABLE;
142
143 if (plat->iprefetch != -EINVAL) {
144 ctl_val &= ~(IPREPETCH_MSK);
145 ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
146 }
147
148 if (plat->dprefetch != -EINVAL) {
149 ctl_val &= ~(DPREPETCH_MSK);
150 ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
151 }
152
153 if (plat->tram_ctl[0] != -EINVAL) {
154 ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
155 ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
156 ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
157 }
158
159 if (plat->dram_ctl[0] != -EINVAL) {
160 ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
161 ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
162 ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
163 }
164
165 writel(ctl_val, &regs->control);
166
167 return 0;
168}
169
170static const struct udevice_id v5l2_cache_ids[] = {
171 { .compatible = "v5l2cache" },
172 {}
173};
174
175static const struct cache_ops v5l2_cache_ops = {
176 .enable = v5l2_enable,
177 .disable = v5l2_disable,
178};
179
180U_BOOT_DRIVER(v5l2_cache) = {
181 .name = "v5l2_cache",
182 .id = UCLASS_CACHE,
183 .of_match = v5l2_cache_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700184 .of_to_plat = v5l2_of_to_plat,
Rick Chen4fa42672019-08-28 18:46:06 +0800185 .probe = v5l2_probe,
Simon Glasscaa4daa2020-12-03 16:55:18 -0700186 .plat_auto = sizeof(struct v5l2_plat),
Rick Chen4fa42672019-08-28 18:46:06 +0800187 .ops = &v5l2_cache_ops,
188 .flags = DM_FLAG_PRE_RELOC,
189};