blob: 4551ed87db7abf71f974549ad33996d2c7384d00 [file] [log] [blame]
Kumar Gala46ff4f12008-08-26 15:01:34 -05001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
10#include <asm/io.h>
York Sun5614e712013-09-30 09:22:09 -070011#include <fsl_ddr_sdram.h>
Kumar Gala46ff4f12008-08-26 15:01:34 -050012
13#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
14#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
15#endif
16
17void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
York Sunc63e1372013-06-25 11:37:48 -070018 unsigned int ctrl_num, int step)
Kumar Gala46ff4f12008-08-26 15:01:34 -050019{
20 unsigned int i;
York Sun9a17eb52013-11-18 10:29:32 -080021 struct ccsr_ddr __iomem *ddr;
Kumar Gala46ff4f12008-08-26 15:01:34 -050022
23 switch (ctrl_num) {
24 case 0:
York Sun5614e712013-09-30 09:22:09 -070025 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
Kumar Gala46ff4f12008-08-26 15:01:34 -050026 break;
27 case 1:
York Sun5614e712013-09-30 09:22:09 -070028 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
Kumar Gala46ff4f12008-08-26 15:01:34 -050029 break;
30 default:
31 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
32 return;
33 }
34
35 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
36 if (i == 0) {
37 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
Kumar Gala46ff4f12008-08-26 15:01:34 -050038 out_be32(&ddr->cs0_config, regs->cs[i].config);
39
40 } else if (i == 1) {
41 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
42 out_be32(&ddr->cs1_config, regs->cs[i].config);
43
44 } else if (i == 2) {
45 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
46 out_be32(&ddr->cs2_config, regs->cs[i].config);
47
48 } else if (i == 3) {
49 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
50 out_be32(&ddr->cs3_config, regs->cs[i].config);
51 }
52 }
53
54 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
55 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
56 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
57 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
58 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
Peter Tysere7ee23e2009-07-17 10:14:45 -050059 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
Kumar Gala46ff4f12008-08-26 15:01:34 -050060 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
York Sun9a17eb52013-11-18 10:29:32 -080061 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
Kumar Gala46ff4f12008-08-26 15:01:34 -050062 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
63 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
64 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
65 out_be32(&ddr->init_addr, regs->ddr_init_addr);
66 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
67
68 debug("before go\n");
69
70 /*
71 * 200 painful micro-seconds must elapse between
72 * the DDR clock setup and the DDR config enable.
73 */
74 udelay(200);
75 asm volatile("sync;isync");
76
Peter Tysere7ee23e2009-07-17 10:14:45 -050077 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
Kumar Gala46ff4f12008-08-26 15:01:34 -050078
79 /*
80 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
81 */
82 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
83 udelay(10000); /* throttle polling rate */
84 }
85}