blob: 605142eab0355d16bc9433b35c9f27056bc2fceb [file] [log] [blame]
Sam Shiha537fa42020-02-21 21:01:46 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
4 *
5 * Author: Sam Shih <sam.shih@mediatek.com>
6 */
7
8#include <common.h>
9#include <clk.h>
10#include <dm.h>
11#include <pwm.h>
12#include <div64.h>
13#include <linux/bitops.h>
14#include <linux/io.h>
15
16/* PWM registers and bits definitions */
17#define PWMCON 0x00
18#define PWMHDUR 0x04
19#define PWMLDUR 0x08
20#define PWMGDUR 0x0c
21#define PWMWAVENUM 0x28
22#define PWMDWIDTH 0x2c
23#define PWM45DWIDTH_FIXUP 0x30
24#define PWMTHRES 0x30
25#define PWM45THRES_FIXUP 0x34
26
27#define PWM_CLK_DIV_MAX 7
28#define MAX_PWM_NUM 8
29
30#define NSEC_PER_SEC 1000000000L
31
Weijie Gao1ac47952022-09-09 19:59:38 +080032enum mtk_pwm_reg_ver {
33 PWM_REG_V1,
34 PWM_REG_V2,
35};
36
37static const unsigned int mtk_pwm_reg_offset_v1[] = {
Sam Shiha537fa42020-02-21 21:01:46 +080038 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
39};
40
Weijie Gao1ac47952022-09-09 19:59:38 +080041static const unsigned int mtk_pwm_reg_offset_v2[] = {
42 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
43};
44
Sam Shiha537fa42020-02-21 21:01:46 +080045struct mtk_pwm_soc {
46 unsigned int num_pwms;
47 bool pwm45_fixup;
Weijie Gao1ac47952022-09-09 19:59:38 +080048 enum mtk_pwm_reg_ver reg_ver;
Sam Shiha537fa42020-02-21 21:01:46 +080049};
50
51struct mtk_pwm_priv {
52 void __iomem *base;
53 struct clk top_clk;
54 struct clk main_clk;
55 struct clk pwm_clks[MAX_PWM_NUM];
56 const struct mtk_pwm_soc *soc;
57};
58
59static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val)
60{
61 struct mtk_pwm_priv *priv = dev_get_priv(dev);
Weijie Gao1ac47952022-09-09 19:59:38 +080062 u32 offset;
63
64 switch (priv->soc->reg_ver) {
65 case PWM_REG_V2:
66 offset = mtk_pwm_reg_offset_v2[channel];
67 break;
68
69 default:
70 offset = mtk_pwm_reg_offset_v1[channel];
71 }
Sam Shiha537fa42020-02-21 21:01:46 +080072
73 writel(val, priv->base + offset + reg);
74}
75
76static int mtk_pwm_set_config(struct udevice *dev, uint channel,
77 uint period_ns, uint duty_ns)
78{
79 struct mtk_pwm_priv *priv = dev_get_priv(dev);
80 u32 clkdiv = 0, clksel = 0, cnt_period, cnt_duty,
81 reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
82 u64 resolution;
83 int ret = 0;
84
85 clk_enable(&priv->top_clk);
86 clk_enable(&priv->main_clk);
87 /* Using resolution in picosecond gets accuracy higher */
88 resolution = (u64)NSEC_PER_SEC * 1000;
89 do_div(resolution, clk_get_rate(&priv->pwm_clks[channel]));
90 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
91 while (cnt_period > 8191) {
92 resolution *= 2;
93 clkdiv++;
94 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
95 resolution);
96 if (clkdiv > PWM_CLK_DIV_MAX && clksel == 0) {
97 clksel = 1;
98 clkdiv = 0;
99 resolution = (u64)NSEC_PER_SEC * 1000 * 1625;
100 do_div(resolution,
101 clk_get_rate(&priv->pwm_clks[channel]));
102 cnt_period = DIV_ROUND_CLOSEST_ULL(
103 (u64)period_ns * 1000, resolution);
104 clk_enable(&priv->pwm_clks[channel]);
105 }
106 }
107 if (clkdiv > PWM_CLK_DIV_MAX && clksel == 1) {
108 printf("pwm period %u not supported\n", period_ns);
109 return -EINVAL;
110 }
111 if (priv->soc->pwm45_fixup && channel > 2) {
112 /*
113 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES
114 * from the other PWMs on MT7623.
115 */
116 reg_width = PWM45DWIDTH_FIXUP;
117 reg_thres = PWM45THRES_FIXUP;
118 }
119 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
120 if (clksel == 1)
121 mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | BIT(3) | clkdiv);
122 else
123 mtk_pwm_w32(dev, channel, PWMCON, BIT(15) | clkdiv);
124 mtk_pwm_w32(dev, channel, reg_width, cnt_period);
125 mtk_pwm_w32(dev, channel, reg_thres, cnt_duty);
126
127 return ret;
128};
129
130static int mtk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
131{
132 struct mtk_pwm_priv *priv = dev_get_priv(dev);
133 u32 val = 0;
134
135 val = readl(priv->base);
136 if (enable)
137 val |= BIT(channel);
138 else
139 val &= ~BIT(channel);
140 writel(val, priv->base);
141
142 return 0;
143};
144
145static int mtk_pwm_probe(struct udevice *dev)
146{
147 struct mtk_pwm_priv *priv = dev_get_priv(dev);
148 int ret = 0;
149 int i;
150
151 priv->soc = (struct mtk_pwm_soc *)dev_get_driver_data(dev);
Masahiro Yamada8613c8d2020-07-17 14:36:46 +0900152 priv->base = dev_read_addr_ptr(dev);
Sam Shiha537fa42020-02-21 21:01:46 +0800153 if (!priv->base)
154 return -EINVAL;
155 ret = clk_get_by_name(dev, "top", &priv->top_clk);
156 if (ret < 0)
157 return ret;
158 ret = clk_get_by_name(dev, "main", &priv->main_clk);
159 if (ret < 0)
160 return ret;
161 for (i = 0; i < priv->soc->num_pwms; i++) {
162 char name[8];
163
164 snprintf(name, sizeof(name), "pwm%d", i + 1);
165 ret = clk_get_by_name(dev, name, &priv->pwm_clks[i]);
166 if (ret < 0)
167 return ret;
168 }
169
170 return ret;
171}
172
173static const struct pwm_ops mtk_pwm_ops = {
174 .set_config = mtk_pwm_set_config,
175 .set_enable = mtk_pwm_set_enable,
176};
177
178static const struct mtk_pwm_soc mt7622_data = {
179 .num_pwms = 6,
180 .pwm45_fixup = false,
Weijie Gao1ac47952022-09-09 19:59:38 +0800181 .reg_ver = PWM_REG_V1,
Sam Shiha537fa42020-02-21 21:01:46 +0800182};
183
184static const struct mtk_pwm_soc mt7623_data = {
185 .num_pwms = 5,
186 .pwm45_fixup = true,
Weijie Gao1ac47952022-09-09 19:59:38 +0800187 .reg_ver = PWM_REG_V1,
Sam Shiha537fa42020-02-21 21:01:46 +0800188};
189
190static const struct mtk_pwm_soc mt7629_data = {
191 .num_pwms = 1,
192 .pwm45_fixup = false,
Weijie Gao1ac47952022-09-09 19:59:38 +0800193 .reg_ver = PWM_REG_V1,
194};
195
196static const struct mtk_pwm_soc mt7981_data = {
197 .num_pwms = 2,
198 .pwm45_fixup = false,
199 .reg_ver = PWM_REG_V2,
Sam Shiha537fa42020-02-21 21:01:46 +0800200};
201
Weijie Gaoc986dd92022-09-09 19:59:36 +0800202static const struct mtk_pwm_soc mt7986_data = {
203 .num_pwms = 2,
204 .pwm45_fixup = false,
Weijie Gao1ac47952022-09-09 19:59:38 +0800205 .reg_ver = PWM_REG_V1,
Weijie Gaoc986dd92022-09-09 19:59:36 +0800206};
207
Sam Shiha537fa42020-02-21 21:01:46 +0800208static const struct udevice_id mtk_pwm_ids[] = {
209 { .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
210 { .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
211 { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
Weijie Gao1ac47952022-09-09 19:59:38 +0800212 { .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
Weijie Gaoc986dd92022-09-09 19:59:36 +0800213 { .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
Sam Shiha537fa42020-02-21 21:01:46 +0800214 { }
215};
216
217U_BOOT_DRIVER(mtk_pwm) = {
218 .name = "mtk_pwm",
219 .id = UCLASS_PWM,
220 .of_match = mtk_pwm_ids,
221 .ops = &mtk_pwm_ops,
222 .probe = mtk_pwm_probe,
Simon Glass41575d82020-12-03 16:55:17 -0700223 .priv_auto = sizeof(struct mtk_pwm_priv),
Sam Shiha537fa42020-02-21 21:01:46 +0800224};