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Wang Huan550e3dc2014-09-05 13:52:44 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <fsl_ddr_sdram.h>
9#include <fsl_ddr_dimm_params.h>
10#include "ddr.h"
11
12DECLARE_GLOBAL_DATA_PTR;
13
14void fsl_ddr_board_options(memctl_options_t *popts,
15 dimm_params_t *pdimm,
16 unsigned int ctrl_num)
17{
18 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
19 ulong ddr_freq;
20
21 if (ctrl_num > 3) {
22 printf("Not supported controller number %d\n", ctrl_num);
23 return;
24 }
25 if (!pdimm->n_ranks)
26 return;
27
28 pbsp = udimms[0];
29
30 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
31 * freqency and n_banks specified in board_specific_parameters table.
32 */
33 ddr_freq = get_ddr_freq(0) / 1000000;
34 while (pbsp->datarate_mhz_high) {
35 if (pbsp->n_ranks == pdimm->n_ranks) {
36 if (ddr_freq <= pbsp->datarate_mhz_high) {
37 popts->clk_adjust = pbsp->clk_adjust;
38 popts->wrlvl_start = pbsp->wrlvl_start;
39 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
40 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
41 popts->cpo_override = pbsp->cpo_override;
42 popts->write_data_delay =
43 pbsp->write_data_delay;
44 goto found;
45 }
46 pbsp_highest = pbsp;
47 }
48 pbsp++;
49 }
50
51 if (pbsp_highest) {
52 printf("Error: board specific timing not found for %lu MT/s\n",
53 ddr_freq);
54 printf("Trying to use the highest speed (%u) parameters\n",
55 pbsp_highest->datarate_mhz_high);
56 popts->clk_adjust = pbsp_highest->clk_adjust;
57 popts->wrlvl_start = pbsp_highest->wrlvl_start;
58 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
59 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
60 } else {
61 panic("DIMM is not supported by this board");
62 }
63found:
64 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
65 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
66
67 /* force DDR bus width to 32 bits */
68 popts->data_bus_width = 1;
69 popts->otf_burst_chop_en = 0;
70 popts->burst_length = DDR_BL8;
71
72 /*
73 * Factors to consider for half-strength driver enable:
74 * - number of DIMMs installed
75 */
76 popts->half_strength_driver_enable = 1;
77 /*
78 * Write leveling override
79 */
80 popts->wrlvl_override = 1;
81 popts->wrlvl_sample = 0xf;
Wang Huan550e3dc2014-09-05 13:52:44 +080082
83 /*
84 * Rtt and Rtt_WR override
85 */
86 popts->rtt_override = 0;
87
88 /* Enable ZQ calibration */
89 popts->zq_en = 1;
90
York Sunc7eae7f2014-09-11 13:32:07 -070091#ifdef CONFIG_SYS_FSL_DDR4
92 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
93 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
94 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
95#else
96 popts->cswl_override = DDR_CSWL_CS0;
97
Wang Huan550e3dc2014-09-05 13:52:44 +080098 /* DHC_EN =1, ODT = 75 Ohm */
99 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
100 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
York Sunc7eae7f2014-09-11 13:32:07 -0700101#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800102}
103
104#ifdef CONFIG_SYS_DDR_RAW_TIMING
105dimm_params_t ddr_raw_timing = {
106 .n_ranks = 1,
107 .rank_density = 1073741824u,
108 .capacity = 1073741824u,
109 .primary_sdram_width = 32,
110 .ec_sdram_width = 0,
111 .registered_dimm = 0,
112 .mirrored_dimm = 0,
113 .n_row_addr = 15,
114 .n_col_addr = 10,
115 .n_banks_per_sdram_device = 8,
116 .edc_config = 0,
117 .burst_lengths_bitmask = 0x0c,
118
119 .tckmin_x_ps = 1071,
120 .caslat_x = 0xfe << 4, /* 5,6,7,8 */
121 .taa_ps = 13125,
122 .twr_ps = 15000,
123 .trcd_ps = 13125,
124 .trrd_ps = 7500,
125 .trp_ps = 13125,
126 .tras_ps = 37500,
127 .trc_ps = 50625,
128 .trfc_ps = 160000,
129 .twtr_ps = 7500,
130 .trtp_ps = 7500,
131 .refresh_rate_ps = 7800000,
132 .tfaw_ps = 37500,
133};
134
135int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
136 unsigned int controller_number,
137 unsigned int dimm_number)
138{
139 static const char dimm_model[] = "Fixed DDR on board";
140
141 if (((controller_number == 0) && (dimm_number == 0)) ||
142 ((controller_number == 1) && (dimm_number == 0))) {
143 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
144 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
145 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
146 }
147
148 return 0;
149}
150#endif
151
152phys_size_t initdram(int board_type)
153{
154 phys_size_t dram_size;
155
Alison Wang86949c22014-12-03 15:00:47 +0800156#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
Wang Huan550e3dc2014-09-05 13:52:44 +0800157 puts("Initializing DDR....using SPD\n");
158 dram_size = fsl_ddr_sdram();
Alison Wang86949c22014-12-03 15:00:47 +0800159#else
160 dram_size = fsl_ddr_sdram_size();
161#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800162 return dram_size;
163}
164
165void dram_init_banksize(void)
166{
167 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
168 gd->bd->bi_dram[0].size = gd->ram_size;
169}