| Lokesh Vutla | 00b34e9 | 2018-11-02 19:51:09 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ |
| 4 | */ |
| 5 | |
| 6 | / { |
| 7 | memorycontroller: memorycontroller@0298e000 { |
| 8 | compatible = "ti,am654-ddrss"; |
| 9 | reg = <0x0 0x0298e000 0x0 0x200>, |
| 10 | <0x0 0x02980000 0x0 0x4000>, |
| 11 | <0x0 0x02988000 0x0 0x2000>; |
| 12 | reg-names = "ss", "ctl", "phy"; |
| 13 | clocks = <&k3_clks 20 0>; |
| Lokesh Vutla | 355be91 | 2019-06-07 19:24:47 +0530 | [diff] [blame] | 14 | power-domains = <&k3_pds 20 TI_SCI_PD_SHARED>, |
| 15 | <&k3_pds 244 TI_SCI_PD_SHARED>; |
| Lokesh Vutla | 00b34e9 | 2018-11-02 19:51:09 +0530 | [diff] [blame] | 16 | assigned-clocks = <&k3_clks 20 1>; |
| 17 | assigned-clock-rates = <DDR_PLL_FREQUENCY>; |
| 18 | u-boot,dm-spl; |
| 19 | |
| 20 | ti,ctl-reg = < |
| 21 | DDRCTL_DFIMISC |
| 22 | DDRCTL_DFITMG0 |
| 23 | DDRCTL_DFITMG1 |
| 24 | DDRCTL_DFITMG2 |
| 25 | DDRCTL_INIT0 |
| 26 | DDRCTL_INIT1 |
| 27 | DDRCTL_INIT3 |
| 28 | DDRCTL_INIT4 |
| 29 | DDRCTL_INIT5 |
| 30 | DDRCTL_INIT6 |
| 31 | DDRCTL_INIT7 |
| 32 | DDRCTL_MSTR |
| 33 | DDRCTL_ODTCFG |
| 34 | DDRCTL_ODTMAP |
| 35 | DDRCTL_RANKCTL |
| 36 | DDRCTL_RFSHCTL0 |
| 37 | DDRCTL_RFSHTMG |
| 38 | DDRCTL_ZQCTL0 |
| 39 | DDRCTL_ZQCTL1 |
| 40 | >; |
| 41 | |
| 42 | ti,ctl-crc = < |
| 43 | DDRCTL_CRCPARCTL0 |
| 44 | DDRCTL_CRCPARCTL1 |
| 45 | DDRCTL_CRCPARCTL2 |
| 46 | >; |
| 47 | |
| 48 | ti,ctl-ecc = < |
| 49 | DDRCTL_ECCCFG0 |
| 50 | >; |
| 51 | |
| 52 | ti,ctl-map = < |
| 53 | DDRCTL_ADDRMAP0 |
| 54 | DDRCTL_ADDRMAP1 |
| 55 | DDRCTL_ADDRMAP2 |
| 56 | DDRCTL_ADDRMAP3 |
| 57 | DDRCTL_ADDRMAP4 |
| 58 | DDRCTL_ADDRMAP5 |
| 59 | DDRCTL_ADDRMAP6 |
| 60 | DDRCTL_ADDRMAP7 |
| 61 | DDRCTL_ADDRMAP8 |
| 62 | DDRCTL_ADDRMAP9 |
| 63 | DDRCTL_ADDRMAP10 |
| 64 | DDRCTL_ADDRMAP11 |
| 65 | DDRCTL_DQMAP0 |
| 66 | DDRCTL_DQMAP1 |
| 67 | DDRCTL_DQMAP4 |
| 68 | DDRCTL_DQMAP5 |
| 69 | >; |
| 70 | |
| 71 | ti,ctl-pwr = < |
| 72 | DDRCTL_PWRCTL |
| 73 | >; |
| 74 | |
| 75 | ti,ctl-timing = < |
| 76 | DDRCTL_DRAMTMG0 |
| 77 | DDRCTL_DRAMTMG1 |
| 78 | DDRCTL_DRAMTMG2 |
| 79 | DDRCTL_DRAMTMG3 |
| 80 | DDRCTL_DRAMTMG4 |
| 81 | DDRCTL_DRAMTMG5 |
| 82 | DDRCTL_DRAMTMG6 |
| 83 | DDRCTL_DRAMTMG7 |
| 84 | DDRCTL_DRAMTMG8 |
| 85 | DDRCTL_DRAMTMG9 |
| 86 | DDRCTL_DRAMTMG11 |
| 87 | DDRCTL_DRAMTMG12 |
| 88 | DDRCTL_DRAMTMG13 |
| 89 | DDRCTL_DRAMTMG14 |
| 90 | DDRCTL_DRAMTMG15 |
| 91 | DDRCTL_DRAMTMG17 |
| 92 | >; |
| 93 | |
| 94 | ti,phy-cfg = < |
| 95 | DDRPHY_DCR |
| 96 | DDRPHY_DSGCR |
| 97 | DDRPHY_DX0GCR0 |
| 98 | DDRPHY_DX0GCR1 |
| 99 | DDRPHY_DX0GCR2 |
| 100 | DDRPHY_DX0GCR3 |
| 101 | DDRPHY_DX0GCR4 |
| 102 | DDRPHY_DX0GCR5 |
| 103 | DDRPHY_DX0GTR0 |
| 104 | DDRPHY_DX1GCR0 |
| 105 | DDRPHY_DX1GCR1 |
| 106 | DDRPHY_DX1GCR2 |
| 107 | DDRPHY_DX1GCR3 |
| 108 | DDRPHY_DX1GCR4 |
| 109 | DDRPHY_DX1GCR5 |
| 110 | DDRPHY_DX1GTR0 |
| 111 | DDRPHY_DX2GCR0 |
| 112 | DDRPHY_DX2GCR1 |
| 113 | DDRPHY_DX2GCR2 |
| 114 | DDRPHY_DX2GCR3 |
| 115 | DDRPHY_DX2GCR4 |
| 116 | DDRPHY_DX2GCR5 |
| 117 | DDRPHY_DX2GTR0 |
| 118 | DDRPHY_DX3GCR0 |
| 119 | DDRPHY_DX3GCR1 |
| 120 | DDRPHY_DX3GCR2 |
| 121 | DDRPHY_DX3GCR3 |
| 122 | DDRPHY_DX3GCR4 |
| 123 | DDRPHY_DX3GCR5 |
| 124 | DDRPHY_DX3GTR0 |
| 125 | DDRPHY_DX4GCR0 |
| 126 | DDRPHY_DX4GCR1 |
| 127 | DDRPHY_DX4GCR2 |
| 128 | DDRPHY_DX4GCR3 |
| 129 | DDRPHY_DX4GCR4 |
| 130 | DDRPHY_DX4GCR5 |
| 131 | DDRPHY_DX4GTR0 |
| 132 | DDRPHY_DX8SL0DXCTL2 |
| 133 | DDRPHY_DX8SL0IOCR |
| 134 | DDRPHY_DX8SL0PLLCR0 |
| 135 | DDRPHY_DX8SL1DXCTL2 |
| 136 | DDRPHY_DX8SL1IOCR |
| 137 | DDRPHY_DX8SL1PLLCR0 |
| 138 | DDRPHY_DX8SL2DXCTL2 |
| 139 | DDRPHY_DX8SL2IOCR |
| 140 | DDRPHY_DX8SL2PLLCR0 |
| 141 | DDRPHY_DXCCR |
| 142 | DDRPHY_ODTCR |
| 143 | DDRPHY_PGCR0 |
| 144 | DDRPHY_PGCR1 |
| 145 | DDRPHY_PGCR2 |
| 146 | DDRPHY_PGCR3 |
| 147 | DDRPHY_PGCR5 |
| 148 | DDRPHY_PGCR6 |
| 149 | >; |
| 150 | |
| 151 | ti,phy-ctl = < |
| 152 | DDRPHY_DTCR0 |
| 153 | DDRPHY_DTCR1 |
| 154 | DDRPHY_MR0 |
| 155 | DDRPHY_MR1 |
| 156 | DDRPHY_MR2 |
| 157 | DDRPHY_MR3 |
| 158 | DDRPHY_MR4 |
| 159 | DDRPHY_MR5 |
| 160 | DDRPHY_MR6 |
| 161 | DDRPHY_MR11 |
| 162 | DDRPHY_MR12 |
| 163 | DDRPHY_MR13 |
| 164 | DDRPHY_MR14 |
| 165 | DDRPHY_MR22 |
| 166 | DDRPHY_PLLCR0 |
| 167 | DDRPHY_VTCR0 |
| 168 | >; |
| 169 | |
| 170 | ti,phy-ioctl = < |
| 171 | DDRPHY_ACIOCR5 |
| 172 | DDRPHY_IOVCR0 |
| 173 | >; |
| 174 | |
| 175 | ti,phy-timing = < |
| 176 | DDRPHY_DTPR0 |
| 177 | DDRPHY_DTPR1 |
| 178 | DDRPHY_DTPR2 |
| 179 | DDRPHY_DTPR3 |
| 180 | DDRPHY_DTPR4 |
| 181 | DDRPHY_DTPR5 |
| 182 | DDRPHY_DTPR6 |
| 183 | DDRPHY_PTR2 |
| 184 | DDRPHY_PTR3 |
| 185 | DDRPHY_PTR4 |
| 186 | DDRPHY_PTR5 |
| 187 | DDRPHY_PTR6 |
| 188 | >; |
| 189 | |
| 190 | ti,phy-zq = < |
| 191 | DDRPHY_ZQ0PR0 |
| 192 | DDRPHY_ZQ1PR0 |
| 193 | DDRPHY_ZQCR |
| 194 | >; |
| 195 | }; |
| 196 | }; |