blob: cb5b8f1a860b0f2b9ec7100d4f878b0cd8e45628 [file] [log] [blame]
Masahiro Yamada509eb672014-11-26 18:33:59 +09001/*
2 * Device Tree Source for UniPhier PH1-Pro4 SoC
3 *
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +09004 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada509eb672014-11-26 18:33:59 +09005 *
Masahiro Yamada13b2ba12015-06-30 18:27:01 +09006 * SPDX-License-Identifier: GPL-2.0+ X11
Masahiro Yamada509eb672014-11-26 18:33:59 +09007 */
8
Masahiro Yamada8f062432015-12-16 10:54:07 +09009/include/ "uniphier-common32.dtsi"
Masahiro Yamada509eb672014-11-26 18:33:59 +090010
11/ {
Masahiro Yamada6462cde2015-03-11 15:54:46 +090012 compatible = "socionext,ph1-pro4";
Masahiro Yamada509eb672014-11-26 18:33:59 +090013
14 cpus {
Masahiro Yamada509eb672014-11-26 18:33:59 +090015 #address-cells = <1>;
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +090016 #size-cells = <0>;
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090017 enable-method = "socionext,uniphier-smp";
Masahiro Yamada509eb672014-11-26 18:33:59 +090018
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
Masahiro Yamada4e1f81d2015-12-16 10:54:08 +090023 next-level-cache = <&l2>;
Masahiro Yamada509eb672014-11-26 18:33:59 +090024 };
25
26 cpu@1 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a9";
29 reg = <1>;
Masahiro Yamada4e1f81d2015-12-16 10:54:08 +090030 next-level-cache = <&l2>;
Masahiro Yamada509eb672014-11-26 18:33:59 +090031 };
32 };
33
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090034 clocks {
35 arm_timer_clk: arm_timer_clk {
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
39 };
Masahiro Yamadad243c182015-08-28 22:33:13 +090040
41 uart_clk: uart_clk {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <73728000>;
45 };
46
47 i2c_clk: i2c_clk {
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 clock-frequency = <50000000>;
51 };
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090052 };
Masahiro Yamada8f062432015-12-16 10:54:07 +090053};
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090054
Masahiro Yamada8f062432015-12-16 10:54:07 +090055&soc {
Masahiro Yamada4e1f81d2015-12-16 10:54:08 +090056 l2: l2-cache@500c0000 {
57 compatible = "socionext,uniphier-system-cache";
58 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
59 interrupts = <0 174 4>, <0 175 4>;
60 cache-unified;
61 cache-size = <(768 * 1024)>;
62 cache-sets = <256>;
63 cache-line-size = <128>;
64 cache-level = <2>;
65 };
66
Masahiro Yamada8f062432015-12-16 10:54:07 +090067 i2c0: i2c@58780000 {
68 compatible = "socionext,uniphier-fi2c";
69 status = "disabled";
70 reg = <0x58780000 0x80>;
Masahiro Yamada509eb672014-11-26 18:33:59 +090071 #address-cells = <1>;
Masahiro Yamada8f062432015-12-16 10:54:07 +090072 #size-cells = <0>;
73 interrupts = <0 41 4>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_i2c0>;
76 clocks = <&i2c_clk>;
77 clock-frequency = <100000>;
78 };
Masahiro Yamadaedcfaeb2015-06-30 18:27:00 +090079
Masahiro Yamada8f062432015-12-16 10:54:07 +090080 i2c1: i2c@58781000 {
81 compatible = "socionext,uniphier-fi2c";
82 status = "disabled";
83 reg = <0x58781000 0x80>;
84 #address-cells = <1>;
85 #size-cells = <0>;
86 interrupts = <0 42 4>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_i2c1>;
89 clocks = <&i2c_clk>;
90 clock-frequency = <100000>;
91 };
Masahiro Yamada625177d2014-11-26 18:34:00 +090092
Masahiro Yamada8f062432015-12-16 10:54:07 +090093 i2c2: i2c@58782000 {
94 compatible = "socionext,uniphier-fi2c";
95 status = "disabled";
96 reg = <0x58782000 0x80>;
97 #address-cells = <1>;
98 #size-cells = <0>;
99 interrupts = <0 43 4>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c2>;
102 clocks = <&i2c_clk>;
103 clock-frequency = <100000>;
104 };
Masahiro Yamada625177d2014-11-26 18:34:00 +0900105
Masahiro Yamada8f062432015-12-16 10:54:07 +0900106 i2c3: i2c@58783000 {
107 compatible = "socionext,uniphier-fi2c";
108 status = "disabled";
109 reg = <0x58783000 0x80>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 interrupts = <0 44 4>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_i2c3>;
115 clocks = <&i2c_clk>;
116 clock-frequency = <100000>;
117 };
Masahiro Yamada625177d2014-11-26 18:34:00 +0900118
Masahiro Yamada8f062432015-12-16 10:54:07 +0900119 /* i2c4 does not exist */
Masahiro Yamada625177d2014-11-26 18:34:00 +0900120
Masahiro Yamada8f062432015-12-16 10:54:07 +0900121 /* chip-internal connection for DMD */
122 i2c5: i2c@58785000 {
123 compatible = "socionext,uniphier-fi2c";
124 reg = <0x58785000 0x80>;
125 #address-cells = <1>;
126 #size-cells = <0>;
127 interrupts = <0 25 4>;
128 clocks = <&i2c_clk>;
129 clock-frequency = <400000>;
130 };
Masahiro Yamada149c7512014-11-26 18:34:01 +0900131
Masahiro Yamada8f062432015-12-16 10:54:07 +0900132 /* chip-internal connection for HDMI */
133 i2c6: i2c@58786000 {
134 compatible = "socionext,uniphier-fi2c";
135 reg = <0x58786000 0x80>;
136 #address-cells = <1>;
137 #size-cells = <0>;
138 interrupts = <0 26 4>;
139 clocks = <&i2c_clk>;
140 clock-frequency = <400000>;
141 };
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900142
Masahiro Yamada8f062432015-12-16 10:54:07 +0900143 usb2: usb@5a800100 {
144 compatible = "socionext,uniphier-ehci", "generic-ehci";
145 status = "disabled";
146 reg = <0x5a800100 0x100>;
147 interrupts = <0 80 4>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_usb2>;
Masahiro Yamada49dde452016-02-02 21:11:37 +0900150 clocks = <&mio 3>, <&mio 6>;
Masahiro Yamada8f062432015-12-16 10:54:07 +0900151 };
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900152
Masahiro Yamada8f062432015-12-16 10:54:07 +0900153 usb3: usb@5a810100 {
154 compatible = "socionext,uniphier-ehci", "generic-ehci";
155 status = "disabled";
156 reg = <0x5a810100 0x100>;
Masahiro Yamada4e1f81d2015-12-16 10:54:08 +0900157 interrupts = <0 81 4>;
Masahiro Yamada8f062432015-12-16 10:54:07 +0900158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_usb3>;
Masahiro Yamada49dde452016-02-02 21:11:37 +0900160 clocks = <&mio 4>, <&mio 6>;
Masahiro Yamada8f062432015-12-16 10:54:07 +0900161 };
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900162
Masahiro Yamada8f062432015-12-16 10:54:07 +0900163 usb0: usb@65a00000 {
164 compatible = "socionext,uniphier-xhci", "generic-xhci";
165 status = "disabled";
166 reg = <0x65a00000 0x100>;
Masahiro Yamada4e1f81d2015-12-16 10:54:08 +0900167 interrupts = <0 134 4>;
Masahiro Yamada8f062432015-12-16 10:54:07 +0900168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_usb0>;
Masahiro Yamada8f062432015-12-16 10:54:07 +0900170 };
Masahiro Yamadaf5fd7af2014-12-06 00:03:23 +0900171
Masahiro Yamada8f062432015-12-16 10:54:07 +0900172 usb1: usb@65c00000 {
173 compatible = "socionext,uniphier-xhci", "generic-xhci";
174 status = "disabled";
175 reg = <0x65c00000 0x100>;
Masahiro Yamada4e1f81d2015-12-16 10:54:08 +0900176 interrupts = <0 137 4>;
Masahiro Yamada8f062432015-12-16 10:54:07 +0900177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_usb1>;
Masahiro Yamada509eb672014-11-26 18:33:59 +0900179 };
180};
Masahiro Yamadad243c182015-08-28 22:33:13 +0900181
Masahiro Yamadacc336092016-02-02 21:11:33 +0900182&refclk {
183 clock-frequency = <25000000>;
184};
185
Masahiro Yamada8f062432015-12-16 10:54:07 +0900186&serial0 {
187 clock-frequency = <73728000>;
188};
189
190&serial1 {
191 clock-frequency = <73728000>;
192};
193
194&serial2 {
195 clock-frequency = <73728000>;
196};
197
198&serial3 {
199 clock-frequency = <73728000>;
200};
201
Masahiro Yamadaaa37aba2016-02-02 21:11:36 +0900202&mio {
203 compatible = "socionext,ph1-pro4-mioctrl";
204 clock-names = "stdmac", "ehci";
205 clocks = <&sysctrl 10>, <&sysctrl 18>;
206};
207
Masahiro Yamada9fbb2f72016-02-02 21:11:35 +0900208&peri {
209 compatible = "socionext,ph1-pro4-perictrl";
210 clock-names = "uart", "fi2c";
211 clocks = <&sysctrl 3>, <&sysctrl 4>;
212};
213
Masahiro Yamada8f062432015-12-16 10:54:07 +0900214&pinctrl {
215 compatible = "socionext,ph1-pro4-pinctrl", "syscon";
216};
Masahiro Yamada233812a2016-02-02 21:11:34 +0900217
218&sysctrl {
219 compatible = "socionext,ph1-pro4-sysctrl";
220};