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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jmonkman@adventnetworks.com>
12 *
13 * (C) Copyright 2001
14 * Advent Networks, Inc. <http://www.adventnetworks.com>
15 * Oliver Brown <obrown@adventnetworks.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36/*********************************************************************/
37/* DESCRIPTION:
38 * This file contains the board configuartion for the GW8260 board.
39 *
40 * MODULE DEPENDENCY:
41 * None
42 *
43 * RESTRICTIONS/LIMITATIONS:
44 * None
45 *
46 * Copyright (c) 2001, Advent Networks, Inc.
47 */
48/*********************************************************************/
49
50#ifndef __CONFIG_H
51#define __CONFIG_H
52
Wolfgang Denk2ae18242010-10-06 09:05:45 +020053#define CONFIG_SYS_TEXT_BASE 0x40000000
54
wdenkfe8c2802002-11-03 00:38:21 +000055/* Enable debug prints */
wdenkfe8c2802002-11-03 00:38:21 +000056#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
57
58/* What is the oscillator's (UX2) frequency in Hz? */
59#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
60
61/*-----------------------------------------------------------------------
62 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
63 *-----------------------------------------------------------------------
64 * What should MODCK_H be? It is dependent on the oscillator
65 * frequency, MODCK[1-3], and desired CPM and core frequencies.
66 * Here are some example values (all frequencies are in MHz):
67 *
68 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
69 * ------- ---------- --- --- ---- ----- ----- -----
70 * 0x5 0x5 66 133 133 Open Close Open
71 * 0x5 0x6 66 133 166 Open Open Close
72 * 0x5 0x7 66 133 200 Open Open Open
73 * 0x6 0x0 66 133 233 Close Close Close
74 * 0x6 0x1 66 133 266 Close Close Open
75 * 0x6 0x2 66 133 300 Close Open Close
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_SBC_MODCK_H 0x05
wdenkfe8c2802002-11-03 00:38:21 +000078
79/* Define this if you want to boot from 0x00000100. If you don't define
80 * this, you will need to program the bootloader to 0xfff00000, and
81 * get the hardware reset config words at 0xfe000000. The simplest
82 * way to do that is to program the bootloader at both addresses.
83 * It is suggested that you just let U-Boot live at 0x00000000.
84 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_SBC_BOOT_LOW 1
wdenkfe8c2802002-11-03 00:38:21 +000086
87/* What should the base address of the main FLASH be and how big is
Paul Gortmakerb30d41c2011-09-17 13:47:47 +000088 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
wdenkfe8c2802002-11-03 00:38:21 +000089 * The main FLASH is whichever is connected to *CS0. U-Boot expects
90 * this to be the SIMM.
91 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_FLASH0_BASE 0x40000000
93#define CONFIG_SYS_FLASH0_SIZE 8
wdenkfe8c2802002-11-03 00:38:21 +000094
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095/* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot.
wdenkfe8c2802002-11-03 00:38:21 +000096 * Note: the 'flashchecksum' environment variable must also be set to 'y'.
97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_FLASH_CHECKSUM
wdenkfe8c2802002-11-03 00:38:21 +000099
100/* What should be the base address of SDRAM DIMM and how big is
101 * it (in Mbytes)?
102 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_SDRAM0_BASE 0x00000000
104#define CONFIG_SYS_SDRAM0_SIZE 64
wdenkfe8c2802002-11-03 00:38:21 +0000105
106/*
107 * DRAM tests
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108 * CONFIG_SYS_DRAM_TEST - enables the following tests.
wdenkfe8c2802002-11-03 00:38:21 +0000109 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110 * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
wdenkfe8c2802002-11-03 00:38:21 +0000111 * Environment variable 'test_dram_data' must be
112 * set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
wdenkfe8c2802002-11-03 00:38:21 +0000114 * addressable. Environment variable
115 * 'test_dram_address' must be set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116 * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
wdenkfe8c2802002-11-03 00:38:21 +0000117 * This test takes about 6 minutes to test 64 MB.
118 * Environment variable 'test_dram_walk' must be
119 * set to 'y'.
120 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_DRAM_TEST
122#if defined(CONFIG_SYS_DRAM_TEST)
123#define CONFIG_SYS_DRAM_TEST_DATA
124#define CONFIG_SYS_DRAM_TEST_ADDRESS
125#define CONFIG_SYS_DRAM_TEST_WALK
126#endif /* CONFIG_SYS_DRAM_TEST */
wdenkfe8c2802002-11-03 00:38:21 +0000127
128/*
129 * GW8260 with 16 MB DIMM:
130 *
131 * 0x0000 0000 Exception Vector code, 8k
132 * :
133 * 0x0000 1FFF
134 * 0x0000 2000 Free for Application Use
135 * :
136 * :
137 *
138 * :
139 * :
140 * 0x00F5 FF30 Monitor Stack (Growing downward)
141 * Monitor Stack Buffer (0x80)
142 * 0x00F5 FFB0 Board Info Data
143 * 0x00F6 0000 Malloc Arena
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200144 * : CONFIG_ENV_SECT_SIZE, 256k
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 * : CONFIG_SYS_MALLOC_LEN, 128k
wdenkfe8c2802002-11-03 00:38:21 +0000146 * 0x00FC 0000 RAM Copy of Monitor Code
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147 * : CONFIG_SYS_MONITOR_LEN, 256k
148 * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
wdenkfe8c2802002-11-03 00:38:21 +0000149 */
150
151/*
152 * GW8260 with 64 MB DIMM:
153 *
154 * 0x0000 0000 Exception Vector code, 8k
155 * :
156 * 0x0000 1FFF
157 * 0x0000 2000 Free for Application Use
158 * :
159 * :
160 *
161 * :
162 * :
163 * 0x03F5 FF30 Monitor Stack (Growing downward)
164 * Monitor Stack Buffer (0x80)
165 * 0x03F5 FFB0 Board Info Data
166 * 0x03F6 0000 Malloc Arena
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200167 * : CONFIG_ENV_SECT_SIZE, 256k
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 * : CONFIG_SYS_MALLOC_LEN, 128k
wdenkfe8c2802002-11-03 00:38:21 +0000169 * 0x03FC 0000 RAM Copy of Monitor Code
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170 * : CONFIG_SYS_MONITOR_LEN, 256k
171 * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
wdenkfe8c2802002-11-03 00:38:21 +0000172 */
173
174
175/*
176 * select serial console configuration
177 *
178 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
179 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
180 * for SCC).
181 *
182 * if CONFIG_CONS_NONE is defined, then the serial console routines must
183 * defined elsewhere.
184 */
185#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
186#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
187#undef CONFIG_CONS_NONE /* define if console on neither */
188#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
189
190/*
191 * select ethernet configuration
192 *
193 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
194 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
195 * for FCC)
196 *
197 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500198 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkfe8c2802002-11-03 00:38:21 +0000199 */
200
201#undef CONFIG_ETHER_ON_SCC
202#define CONFIG_ETHER_ON_FCC
203#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
204
205#ifdef CONFIG_ETHER_ON_SCC
206#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
207#endif /* CONFIG_ETHER_ON_SCC */
208
209#ifdef CONFIG_ETHER_ON_FCC
210#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
211#define CONFIG_MII /* MII PHY management */
212#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
213/*
214 * Port pins used for bit-banged MII communictions (if applicable).
215 */
216#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200217
218#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
219 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
220#define MDC_DECLARE MDIO_DECLARE
221
wdenkfe8c2802002-11-03 00:38:21 +0000222#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
223#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
224#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
225
226#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
wdenk8bde7f72003-06-27 21:31:46 +0000227 else iop->pdat &= ~0x00400000
wdenkfe8c2802002-11-03 00:38:21 +0000228
229#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
wdenk8bde7f72003-06-27 21:31:46 +0000230 else iop->pdat &= ~0x00200000
wdenkfe8c2802002-11-03 00:38:21 +0000231
232#define MIIDELAY udelay(1)
233#endif /* CONFIG_ETHER_ON_FCC */
234
235#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
236
237/*
238 * - Rx-CLK is CLK13
239 * - Tx-CLK is CLK14
240 * - Select bus for bd/buffers (see 28-13)
241 * - Enable Full Duplex in FSMR
242 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000243# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
244# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245# define CONFIG_SYS_CPMFCR_RAMTYPE 0
246# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkfe8c2802002-11-03 00:38:21 +0000247
248#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
249
250/*
251 * - Rx-CLK is CLK15
252 * - Tx-CLK is CLK16
253 * - Select bus for bd/buffers (see 28-13)
254 * - Enable Full Duplex in FSMR
255 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000256# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
257# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258# define CONFIG_SYS_CPMFCR_RAMTYPE 0
259# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkfe8c2802002-11-03 00:38:21 +0000260
261#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
262
263/* Define this to reserve an entire FLASH sector (256 KB) for
264 * environment variables. Otherwise, the environment will be
265 * put in the same sector as U-Boot, and changing variables
266 * will erase U-Boot temporarily
267 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200268#define CONFIG_ENV_IN_OWN_SECT
wdenkfe8c2802002-11-03 00:38:21 +0000269
270/* Define to allow the user to overwrite serial and ethaddr */
271#define CONFIG_ENV_OVERWRITE
272
273/* What should the console's baud rate be? */
274#define CONFIG_BAUDRATE 115200
275
276/* Ethernet MAC address - This is set to all zeros to force an
277 * an error if we use BOOTP without setting
278 * the MAC address
279 */
280#define CONFIG_ETHADDR 00:00:00:00:00:00
281
282/* Set to a positive value to delay for running BOOTCOMMAND */
283#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
284
285/* Be selective on what keys can delay or stop the autoboot process
286 * To stop use: " "
287 */
288#define CONFIG_AUTOBOOT_KEYED
Stefan Roesef2302d42008-08-06 14:05:38 +0200289#define CONFIG_AUTOBOOT_PROMPT \
290 "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
wdenkfe8c2802002-11-03 00:38:21 +0000291#define CONFIG_AUTOBOOT_STOP_STR " "
292#undef CONFIG_AUTOBOOT_DELAY_STR
293#define DEBUG_BOOTKEYS 0
294
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500295/*
296 * BOOTP options
wdenkfe8c2802002-11-03 00:38:21 +0000297 */
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500298#define CONFIG_BOOTP_SUBNETMASK
299#define CONFIG_BOOTP_GATEWAY
300#define CONFIG_BOOTP_HOSTNAME
301#define CONFIG_BOOTP_BOOTPATH
302
303#define CONFIG_BOOTP_BOOTFILESIZE
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200304#define CONFIG_BOOTP_DNS
wdenkfe8c2802002-11-03 00:38:21 +0000305
306/* undef this to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_LONGHELP
wdenkfe8c2802002-11-03 00:38:21 +0000308
309/* Monitor Command Prompt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_PROMPT "=> "
wdenkfe8c2802002-11-03 00:38:21 +0000311
Jon Loeliger72eb0ef2007-07-04 22:32:19 -0500312
313/*
314 * Command line configuration.
315 */
316#include <config_cmd_default.h>
317
318#define CONFIG_CMD_BEDBUG
319#define CONFIG_CMD_ELF
320#define CONFIG_CMD_ASKENV
321#define CONFIG_CMD_REGINFO
322#define CONFIG_CMD_IMMAP
323#define CONFIG_CMD_MII
324
325#undef CONFIG_CMD_KGDB
326
wdenkfe8c2802002-11-03 00:38:21 +0000327
328/* Where do the internal registers live? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_IMMR 0xf0000000
wdenkfe8c2802002-11-03 00:38:21 +0000330
331/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_HUSH_PARSER
333#ifdef CONFIG_SYS_HUSH_PARSER
wdenkfe8c2802002-11-03 00:38:21 +0000334#endif
335
336/* What is the address of IO controller */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_IO_BASE 0xe0000000
wdenkfe8c2802002-11-03 00:38:21 +0000338
339/*****************************************************************************
340 *
341 * You should not have to modify any of the following settings
342 *
343 *****************************************************************************/
344
345#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
346#define CONFIG_GW8260 1 /* on an GW8260 Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500347#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkfe8c2802002-11-03 00:38:21 +0000348
wdenkfe8c2802002-11-03 00:38:21 +0000349/*
350 * Miscellaneous configurable options
351 */
Jon Loeliger72eb0ef2007-07-04 22:32:19 -0500352#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000354#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000356#endif
357
358/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
wdenkfe8c2802002-11-03 00:38:21 +0000360
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
wdenkfe8c2802002-11-03 00:38:21 +0000362
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000364
365/* Convert clocks to MHZ when passing board info to kernel.
366 * This must be defined for eariler 2.4 kernels (~2.4.4).
367 */
368#define CONFIG_CLOCKS_IN_MHZ
369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
371#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkfe8c2802002-11-03 00:38:21 +0000372
373
374/* memtest works from the end of the exception vector table
375 * to the end of the DRAM less monitor and malloc area
376 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_MEMTEST_START 0x2000
wdenkfe8c2802002-11-03 00:38:21 +0000378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
wdenkfe8c2802002-11-03 00:38:21 +0000380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
382 + CONFIG_SYS_MALLOC_LEN \
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200383 + CONFIG_ENV_SECT_SIZE \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384 + CONFIG_SYS_STACK_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
387 - CONFIG_SYS_MEM_END_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000388
wdenkfe8c2802002-11-03 00:38:21 +0000389/*
390 * Low Level Configuration Settings
391 * (address mappings, register initial values, etc.)
392 * You should know what you are doing if you make changes here.
393 */
394
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
396#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
397#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
398#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
wdenkfe8c2802002-11-03 00:38:21 +0000399
400/*-----------------------------------------------------------------------
401 * Hard Reset Configuration Words
402 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#if defined(CONFIG_SYS_SBC_BOOT_LOW)
404# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenkfe8c2802002-11-03 00:38:21 +0000405#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
407#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
wdenkfe8c2802002-11-03 00:38:21 +0000408
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409/* get the HRCW ISB field from CONFIG_SYS_IMMR */
410#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
411 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
412 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenkfe8c2802002-11-03 00:38:21 +0000413
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \
wdenk8bde7f72003-06-27 21:31:46 +0000415 HRCW_DPPC11 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416 CONFIG_SYS_SBC_HRCW_IMMR | \
wdenk8bde7f72003-06-27 21:31:46 +0000417 HRCW_MMR00 | \
418 HRCW_LBPC11 | \
419 HRCW_APPC10 | \
420 HRCW_CS10PC00 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
422 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
wdenkfe8c2802002-11-03 00:38:21 +0000423
424/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_HRCW_SLAVE1 0
426#define CONFIG_SYS_HRCW_SLAVE2 0
427#define CONFIG_SYS_HRCW_SLAVE3 0
428#define CONFIG_SYS_HRCW_SLAVE4 0
429#define CONFIG_SYS_HRCW_SLAVE5 0
430#define CONFIG_SYS_HRCW_SLAVE6 0
431#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkfe8c2802002-11-03 00:38:21 +0000432
433/*-----------------------------------------------------------------------
434 * Definitions for initial stack pointer and data area (in DPRAM)
435 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200437#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200438#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkfe8c2802002-11-03 00:38:21 +0000440
441/*-----------------------------------------------------------------------
442 * Start addresses for the final memory configuration
443 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
445 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
wdenkfe8c2802002-11-03 00:38:21 +0000446 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000448
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
450#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000451
452/*
453 * For booting Linux, the board info and command line data
454 * have to be in the first 8 MB of memory, since this is
455 * the maximum mapped by the Linux kernel during initialization.
456 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000458
459/*-----------------------------------------------------------------------
460 * FLASH and environment organization
461 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
463#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
wdenkfe8c2802002-11-03 00:38:21 +0000464
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
466#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
wdenkfe8c2802002-11-03 00:38:21 +0000467
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200468#define CONFIG_ENV_IS_IN_FLASH 1
wdenkfe8c2802002-11-03 00:38:21 +0000469
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200470#ifdef CONFIG_ENV_IN_OWN_SECT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + (256 * 1024))
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200472# define CONFIG_ENV_SECT_SIZE (256 * 1024)
wdenkfe8c2802002-11-03 00:38:21 +0000473#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200474# define CONFIG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475# define CONFIG_ENV_ADD ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200476# define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */
477#endif /* CONFIG_ENV_IN_OWN_SECT */
wdenkfe8c2802002-11-03 00:38:21 +0000478
479/*-----------------------------------------------------------------------
480 * Cache Configuration
481 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
wdenkfe8c2802002-11-03 00:38:21 +0000483
Jon Loeliger72eb0ef2007-07-04 22:32:19 -0500484#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkfe8c2802002-11-03 00:38:21 +0000486#endif
487
488/*-----------------------------------------------------------------------
489 * HIDx - Hardware Implementation-dependent Registers 2-11
490 *-----------------------------------------------------------------------
491 * HID0 also contains cache control - initially enable both caches and
492 * invalidate contents, then the final state leaves only the instruction
493 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
494 * but Soft reset does not.
495 *
496 * HID1 has only read-only information - nothing to set.
497 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
wdenk8bde7f72003-06-27 21:31:46 +0000499 HID0_DCE |\
500 HID0_ICFI |\
501 HID0_DCI |\
502 HID0_IFEM |\
503 HID0_ABE)
wdenkfe8c2802002-11-03 00:38:21 +0000504
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
wdenk8bde7f72003-06-27 21:31:46 +0000506 HID0_IFEM |\
507 HID0_ABE |\
508 HID0_EMCP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200509#define CONFIG_SYS_HID2 0
wdenkfe8c2802002-11-03 00:38:21 +0000510
511/*-----------------------------------------------------------------------
512 * RMR - Reset Mode Register
513 *-----------------------------------------------------------------------
514 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_RMR 0
wdenkfe8c2802002-11-03 00:38:21 +0000516
517/*-----------------------------------------------------------------------
518 * BCR - Bus Configuration 4-25
519 *-----------------------------------------------------------------------
520 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_BCR (BCR_ETM)
wdenkfe8c2802002-11-03 00:38:21 +0000522
523/*-----------------------------------------------------------------------
524 * SIUMCR - SIU Module Configuration 4-31
525 *-----------------------------------------------------------------------
526 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
wdenk8bde7f72003-06-27 21:31:46 +0000528 SIUMCR_L2CPC00 |\
529 SIUMCR_APPC10 |\
530 SIUMCR_MMR00)
wdenkfe8c2802002-11-03 00:38:21 +0000531
532
533/*-----------------------------------------------------------------------
534 * SYPCR - System Protection Control 11-9
535 * SYPCR can only be written once after reset!
536 *-----------------------------------------------------------------------
537 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
538 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200539#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
wdenk8bde7f72003-06-27 21:31:46 +0000540 SYPCR_BMT |\
541 SYPCR_PBME |\
542 SYPCR_LBME |\
543 SYPCR_SWRI |\
544 SYPCR_SWP)
wdenkfe8c2802002-11-03 00:38:21 +0000545
546/*-----------------------------------------------------------------------
547 * TMCNTSC - Time Counter Status and Control 4-40
548 *-----------------------------------------------------------------------
549 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
550 * and enable Time Counter
551 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200552#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
wdenk8bde7f72003-06-27 21:31:46 +0000553 TMCNTSC_ALR |\
554 TMCNTSC_TCF |\
555 TMCNTSC_TCE)
wdenkfe8c2802002-11-03 00:38:21 +0000556
557/*-----------------------------------------------------------------------
558 * PISCR - Periodic Interrupt Status and Control 4-42
559 *-----------------------------------------------------------------------
560 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
561 * Periodic timer
562 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563#define CONFIG_SYS_PISCR (PISCR_PS |\
wdenk8bde7f72003-06-27 21:31:46 +0000564 PISCR_PTF |\
565 PISCR_PTE)
wdenkfe8c2802002-11-03 00:38:21 +0000566
567/*-----------------------------------------------------------------------
568 * SCCR - System Clock Control 9-8
569 *-----------------------------------------------------------------------
570 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200571#define CONFIG_SYS_SCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000572
573/*-----------------------------------------------------------------------
574 * RCCR - RISC Controller Configuration 13-7
575 *-----------------------------------------------------------------------
576 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200577#define CONFIG_SYS_RCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000578
579/*
580 * Initialize Memory Controller:
581 *
582 * Bank Bus Machine PortSz Device
583 * ---- --- ------- ------ ------
584 * 0 60x GPCM 32 bit FLASH (SIMM - 4MB)
585 * 1 60x GPCM 32 bit unused
586 * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
587 * 3 60x SDRAM 64 bit unused
588 * 4 Local GPCM 8 bit IO (on board - 64k)
589 * 5 60x GPCM 8 bit unused
590 * 6 60x GPCM 8 bit unused
591 * 7 60x GPCM 8 bit unused
592 *
593 */
594
595/*-----------------------------------------------------------------------
596 * BR0 - Base Register
597 * Ref: Section 10.3.1 on page 10-14
598 * OR0 - Option Register
599 * Ref: Section 10.3.2 on page 10-18
600 *-----------------------------------------------------------------------
601 */
602
603/* Bank 0,1 - FLASH SIMM
604 *
605 * This expects the FLASH SIMM to be connected to *CS0
606 * It consists of 4 AM29F016D parts.
607 *
608 * Note: For the 8 MB SIMM, *CS1 is unused.
609 */
610
611/* BR0 is configured as follows:
612 *
613 * - Base address of 0x40000000
614 * - 32 bit port size
615 * - Data errors checking is disabled
616 * - Read and write access
617 * - GPCM 60x bus
618 * - Access are handled by the memory controller according to MSEL
619 * - Not used for atomic operations
620 * - No data pipelining is done
621 * - Valid
622 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200623#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000624 BRx_PS_32 |\
625 BRx_MS_GPCM_P |\
626 BRx_V)
wdenkfe8c2802002-11-03 00:38:21 +0000627
628/* OR0 is configured as follows:
629 *
630 * - 8 MB
631 * - *BCTL0 is asserted upon access to the current memory bank
632 * - *CW / *WE are negated a quarter of a clock earlier
633 * - *CS is output at the same time as the address lines
634 * - Uses a clock cycle length of 5
635 * - *PSDVAL is generated internally by the memory controller
636 * unless *GTA is asserted earlier externally.
637 * - Relaxed timing is generated by the GPCM for accesses
638 * initiated to this memory region.
639 * - One idle clock is inserted between a read access from the
640 * current bank and the next access.
641 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200642#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000643 ORxG_CSNT |\
644 ORxG_ACS_DIV1 |\
645 ORxG_SCY_5_CLK |\
646 ORxG_TRLX |\
647 ORxG_EHTR)
wdenkfe8c2802002-11-03 00:38:21 +0000648
649/*-----------------------------------------------------------------------
650 * BR2 - Base Register
651 * Ref: Section 10.3.1 on page 10-14
652 * OR2 - Option Register
653 * Ref: Section 10.3.2 on page 10-16
654 *-----------------------------------------------------------------------
655 */
656
657/* Bank 2 - SDRAM DIMM
658 *
659 * 16MB DIMM: P/N
660 * 64MB DIMM: P/N 1W-8864X8-4-P1-EST or
661 * MT4LSDT864AG-10EB1 (Micron)
662 *
663 * Note: *CS3 is unused for this DIMM
664 */
665
666/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
667 *
668 * - Base address of 0x00000000
669 * - 64 bit port size (60x bus only)
670 * - Data errors checking is disabled
671 * - Read and write access
672 * - SDRAM 60x bus
673 * - Access are handled by the memory controller according to MSEL
674 * - Not used for atomic operations
675 * - No data pipelining is done
676 * - Valid
677 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200678#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000679 BRx_PS_64 |\
680 BRx_MS_SDRAM_P |\
681 BRx_V)
wdenkfe8c2802002-11-03 00:38:21 +0000682
683/* With a 16 MB DIMM, the OR2 is configured as follows:
684 *
685 * - 16 MB
686 * - 2 internal banks per device
687 * - Row start address bit is A9 with PSDMR[PBI] = 0
688 * - 11 row address lines
689 * - Back-to-back page mode
690 * - Internal bank interleaving within save device enabled
691 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200692#if (CONFIG_SYS_SDRAM0_SIZE == 16)
693#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000694 ORxS_BPD_2 |\
695 ORxS_ROWST_PBI0_A9 |\
696 ORxS_NUMR_11)
wdenkfe8c2802002-11-03 00:38:21 +0000697
698/* With a 16 MB DIMM, the PSDMR is configured as follows:
699 *
700 * - Page Based Interleaving,
701 * - Refresh Enable,
702 * - Address Multiplexing where A5 is output on A14 pin
703 * (A6 on A15, and so on),
704 * - use address pins A16-A18 as bank select,
705 * - A9 is output on SDA10 during an ACTIVATE command,
706 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
707 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
708 * is 3 clocks,
709 * - earliest timing for READ/WRITE command after ACTIVATE command is
710 * 2 clocks,
711 * - earliest timing for PRECHARGE after last data was read is 1 clock,
712 * - earliest timing for PRECHARGE after last data was written is 1 clock,
713 * - CAS Latency is 2.
714 */
715
716/*-----------------------------------------------------------------------
717 * PSDMR - 60x Bus SDRAM Mode Register
718 * Ref: Section 10.3.3 on page 10-21
719 *-----------------------------------------------------------------------
720 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200721#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenk8bde7f72003-06-27 21:31:46 +0000722 PSDMR_SDAM_A14_IS_A5 |\
723 PSDMR_BSMA_A16_A18 |\
724 PSDMR_SDA10_PBI0_A9 |\
725 PSDMR_RFRC_7_CLK |\
726 PSDMR_PRETOACT_3W |\
727 PSDMR_ACTTORW_2W |\
728 PSDMR_LDOTOPRE_1C |\
729 PSDMR_WRC_1C |\
730 PSDMR_CL_2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200731#endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */
wdenkfe8c2802002-11-03 00:38:21 +0000732
733/* With a 64 MB DIMM, the OR2 is configured as follows:
734 *
735 * - 64 MB
736 * - 4 internal banks per device
737 * - Row start address bit is A8 with PSDMR[PBI] = 0
738 * - 12 row address lines
739 * - Back-to-back page mode
740 * - Internal bank interleaving within save device enabled
741 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200742#if (CONFIG_SYS_SDRAM0_SIZE == 64)
743#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000744 ORxS_BPD_4 |\
745 ORxS_ROWST_PBI0_A8 |\
746 ORxS_NUMR_12)
wdenkfe8c2802002-11-03 00:38:21 +0000747
748/* With a 64 MB DIMM, the PSDMR is configured as follows:
749 *
750 * - Page Based Interleaving,
751 * - Refresh Enable,
752 * - Address Multiplexing where A5 is output on A14 pin
753 * (A6 on A15, and so on),
754 * - use address pins A14-A16 as bank select,
755 * - A9 is output on SDA10 during an ACTIVATE command,
756 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
757 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
758 * is 3 clocks,
759 * - earliest timing for READ/WRITE command after ACTIVATE command is
760 * 2 clocks,
761 * - earliest timing for PRECHARGE after last data was read is 1 clock,
762 * - earliest timing for PRECHARGE after last data was written is 1 clock,
763 * - CAS Latency is 2.
764 */
765
766/*-----------------------------------------------------------------------
767 * PSDMR - 60x Bus SDRAM Mode Register
768 * Ref: Section 10.3.3 on page 10-21
769 *-----------------------------------------------------------------------
770 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200771#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenk8bde7f72003-06-27 21:31:46 +0000772 PSDMR_SDAM_A14_IS_A5 |\
773 PSDMR_BSMA_A14_A16 |\
774 PSDMR_SDA10_PBI0_A9 |\
775 PSDMR_RFRC_7_CLK |\
776 PSDMR_PRETOACT_3W |\
777 PSDMR_ACTTORW_2W |\
778 PSDMR_LDOTOPRE_1C |\
779 PSDMR_WRC_1C |\
780 PSDMR_CL_2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200781#endif /* (CONFIG_SYS_SDRAM0_SIZE == 64) */
wdenkfe8c2802002-11-03 00:38:21 +0000782
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200783#define CONFIG_SYS_PSRT 0x0e
784#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
wdenkfe8c2802002-11-03 00:38:21 +0000785
786
787/*-----------------------------------------------------------------------
788 * BR4 - Base Register
789 * Ref: Section 10.3.1 on page 10-14
790 * OR4 - Option Register
791 * Ref: Section 10.3.2 on page 10-18
792 *-----------------------------------------------------------------------
793 */
794/* Bank 4 - Onboard Memory Mapped IO controller
795 *
796 * This expects the onboard IO controller to connected to *CS4 and
797 * the local bus.
798 * - Base address of 0xe0000000
799 * - 8 bit port size (local bus only)
800 * - Read and write access
801 * - GPCM local bus
802 * - Not used for atomic operations
803 * - No data pipelining is done
804 * - Valid
805 * - extended hold time
806 * - 11 wait states
807 */
808
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200809#ifdef CONFIG_SYS_IO_BASE
810# define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000811 BRx_PS_8 |\
812 BRx_MS_GPCM_L |\
813 BRx_V)
wdenkfe8c2802002-11-03 00:38:21 +0000814
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200815# define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
wdenk8bde7f72003-06-27 21:31:46 +0000816 ORxG_SCY_11_CLK |\
817 ORxG_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200818#endif /* CONFIG_SYS_IO_BASE */
wdenkfe8c2802002-11-03 00:38:21 +0000819#endif /* __CONFIG_H */