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Stefan Roese899620c2006-08-15 14:22:35 +02001/*
Stefan Roese94627322008-03-19 10:23:43 +01002 * (C) Copyright 2006-2008
Stefan Roese899620c2006-08-15 14:22:35 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese899620c2006-08-15 14:22:35 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*-----------------------------------------------------------------------
12 * High Level Configuration Options
13 *----------------------------------------------------------------------*/
14#define CONFIG_ALPR 1 /* Board is ebony */
15#define CONFIG_440GX 1 /* Specifc GX support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020016#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roese899620c2006-08-15 14:22:35 +020017#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Stefan Roese1c2ce222006-11-27 14:12:17 +010018#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020019
20#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
21
Stefan Roese1c2ce222006-11-27 14:12:17 +010022#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +010023#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */
Stefan Roese899620c2006-08-15 14:22:35 +020024
25/*-----------------------------------------------------------------------
26 * Base addresses -- Note these are effective addresses where the
27 * actual resources get mapped (not physical addresses)
28 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
30#define CONFIG_SYS_FLASH_BASE 0xffe00000 /* start of FLASH */
31#define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */
32#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
33#define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
35#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
36#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
37#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
38#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roese899620c2006-08-15 14:22:35 +020039
40
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
42#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
Stefan Roese899620c2006-08-15 14:22:35 +020043
44/*-----------------------------------------------------------------------
45 * Initial RAM & stack pointer (placed in internal SRAM)
46 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_TEMP_STACK_OCM 1
48#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
49#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +020050#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Stefan Roese899620c2006-08-15 14:22:35 +020051
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020052#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidman800eb092010-09-20 08:51:53 +020053#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Stefan Roese899620c2006-08-15 14:22:35 +020054
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
56#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
Stefan Roese899620c2006-08-15 14:22:35 +020057
58/*-----------------------------------------------------------------------
59 * Serial Port
60 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020061#define CONFIG_CONS_INDEX 2 /* Use UART1 */
62#define CONFIG_SYS_NS16550
63#define CONFIG_SYS_NS16550_SERIAL
64#define CONFIG_SYS_NS16550_REG_SIZE 1
65#define CONFIG_SYS_NS16550_CLK get_serial_clock()
66
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Stefan Roese899620c2006-08-15 14:22:35 +020068#define CONFIG_BAUDRATE 115200
Stefan Roese899620c2006-08-15 14:22:35 +020069
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roese899620c2006-08-15 14:22:35 +020071 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
72
73/*-----------------------------------------------------------------------
Stefan Roese899620c2006-08-15 14:22:35 +020074 * FLASH related
75 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020077#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
79#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
80#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
81#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
82#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Stefan Roese899620c2006-08-15 14:22:35 +020083
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020084#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese899620c2006-08-15 14:22:35 +020085
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020086#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020088#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese899620c2006-08-15 14:22:35 +020089
90/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020091#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
92#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese899620c2006-08-15 14:22:35 +020093
94/*-----------------------------------------------------------------------
95 * DDR SDRAM
96 *----------------------------------------------------------------------*/
97#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
98#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
99#undef CONFIG_SDRAM_ECC /* enable ECC support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_SDRAM_TABLE { \
Stefan Roese899620c2006-08-15 14:22:35 +0200101 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
102 {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
103
104/*-----------------------------------------------------------------------
105 * I2C
106 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000107#define CONFIG_SYS_I2C
108#define CONFIG_SYS_I2C_PPC4XX
109#define CONFIG_SYS_I2C_PPC4XX_CH0
110#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
111#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
112#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
Stefan Roese899620c2006-08-15 14:22:35 +0200113
114/*-----------------------------------------------------------------------
115 * I2C EEPROM (PCF8594C)
116 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
118#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roese899620c2006-08-15 14:22:35 +0200119/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
121#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
Stefan Roese899620c2006-08-15 14:22:35 +0200122 /* 8 byte page write mode using */
123 /* last 3 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
Stefan Roese899620c2006-08-15 14:22:35 +0200125
126#define CONFIG_PREBOOT "echo;" \
Stefan Roese63044302007-01-30 12:51:07 +0100127 "echo Type \"run kernelx\" to boot the system;" \
Stefan Roese899620c2006-08-15 14:22:35 +0200128 "echo"
129
130#undef CONFIG_BOOTARGS
131
132#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100133 "netdev=eth3\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200134 "hostname=alpr\0" \
Stefan Roese94627322008-03-19 10:23:43 +0100135 "fdt_file=alpr/alpr.dtb\0" \
136 "fdt_addr=400000\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200137 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Stefan Roese63044302007-01-30 12:51:07 +0100138 "nfsroot=${serverip}:${rootpath} ${init}\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200139 "ramargs=setenv bootargs root=/dev/ram rw\0" \
140 "addip=setenv bootargs ${bootargs} " \
141 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
142 ":${hostname}:${netdev}:off panic=1\0" \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100143 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
144 "mem=193M\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200145 "flash_nfs=run nfsargs addip addtty;" \
146 "bootm ${kernel_addr}\0" \
147 "flash_self=run ramargs addip addtty;" \
148 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
149 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
Wolfgang Denk93e14592013-10-04 17:43:24 +0200150 "bootm\0" \
Stefan Roese94627322008-03-19 10:23:43 +0100151 "net_nfs_fdt=tftp 200000 ${bootfile};" \
152 "tftp ${fdt_addr} ${fdt_file};" \
153 "run nfsargs addip addtty;" \
154 "bootm 200000 - ${fdt_addr}\0" \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100155 "rootpath=/opt/projects/alpr/nfs_root\0" \
156 "bootfile=/alpr/uImage\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200157 "kernel_addr=fff00000\0" \
158 "ramdisk_addr=fff10000\0" \
Stefan Roese1c2ce222006-11-27 14:12:17 +0100159 "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200160 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
161 "cp.b 100000 fffc0000 40000;" \
162 "setenv filesize;saveenv\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100163 "upd=run load update\0" \
Stefan Roesef16c1da2007-01-06 15:56:13 +0100164 "ethprime=ppc_4xx_eth3\0" \
165 "ethact=ppc_4xx_eth3\0" \
166 "autoload=no\0" \
167 "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
Stefan Roesef16c1da2007-01-06 15:56:13 +0100168 "load_fpga=fpga load 0 ffe00000 10dd9a\0" \
169 "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
170 "rootfstype=jffs2 init=/sbin/init\0" \
171 "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
172 ";bootm 200000\0" \
173 "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
174 "addtty;bootm 200000\0" \
Stefan Roese63044302007-01-30 12:51:07 +0100175 "kernel1=setenv actkernel 'kernel1';run load_fpga " \
176 "kernel1_mtd\0" \
177 "kernel2=setenv actkernel 'kernel2';run load_fpga " \
178 "kernel2_mtd\0" \
Stefan Roese899620c2006-08-15 14:22:35 +0200179 ""
Stefan Roesef16c1da2007-01-06 15:56:13 +0100180
181#define CONFIG_BOOTCOMMAND "run kernel2"
Stefan Roese899620c2006-08-15 14:22:35 +0200182
Stefan Roese1c2ce222006-11-27 14:12:17 +0100183#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
Stefan Roese899620c2006-08-15 14:22:35 +0200184
185#define CONFIG_BAUDRATE 115200
186
187#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roese899620c2006-08-15 14:22:35 +0200189
Ben Warren96e21f82008-10-27 23:50:15 -0700190#define CONFIG_PPC4xx_EMAC
Stefan Roese899620c2006-08-15 14:22:35 +0200191#define CONFIG_MII 1 /* MII PHY management */
Stefan Roese899620c2006-08-15 14:22:35 +0200192#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
193#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100194#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */
195#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */
Stefan Roese899620c2006-08-15 14:22:35 +0200196#define CONFIG_HAS_ETH0
197#define CONFIG_HAS_ETH1
198#define CONFIG_HAS_ETH2
199#define CONFIG_HAS_ETH3
200#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Stefan Roeseec0c2ec2006-11-27 14:46:06 +0100201#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/
Stefan Roese899620c2006-08-15 14:22:35 +0200202#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Stefan Roese899620c2006-08-15 14:22:35 +0200204
Stefan Roese5bc528f2006-10-07 11:35:25 +0200205#define CONFIG_NETCONSOLE /* include NetConsole support */
206
Stefan Roese899620c2006-08-15 14:22:35 +0200207
Jon Loeliger0b361c92007-07-04 22:31:42 -0500208/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500209 * BOOTP options
210 */
211#define CONFIG_BOOTP_BOOTFILESIZE
212#define CONFIG_BOOTP_BOOTPATH
213#define CONFIG_BOOTP_GATEWAY
214#define CONFIG_BOOTP_HOSTNAME
215
216
217/*
Jon Loeliger0b361c92007-07-04 22:31:42 -0500218 * Command line configuration.
219 */
220#include <config_cmd_default.h>
221
Jon Loeliger0b361c92007-07-04 22:31:42 -0500222#define CONFIG_CMD_DHCP
Jon Loeliger0b361c92007-07-04 22:31:42 -0500223#define CONFIG_CMD_EEPROM
Jon Loeliger0b361c92007-07-04 22:31:42 -0500224#define CONFIG_CMD_FPGA
225#define CONFIG_CMD_I2C
Stefan Roese288991c2010-04-08 09:33:13 +0200226#undef CONFIG_CMD_LOADB
227#undef CONFIG_CMD_LOADS
Jon Loeliger0b361c92007-07-04 22:31:42 -0500228#define CONFIG_CMD_MII
229#define CONFIG_CMD_NAND
230#define CONFIG_CMD_NET
Stefan Roese8c92af72008-12-09 20:08:01 +0100231#undef CONFIG_CMD_NFS
Stefan Roese288991c2010-04-08 09:33:13 +0200232#define CONFIG_CMD_PCI
Stefan Roese899620c2006-08-15 14:22:35 +0200233
234#undef CONFIG_WATCHDOG /* watchdog disabled */
235
236/*
237 * Miscellaneous configurable options
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger0b361c92007-07-04 22:31:42 -0500240#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese899620c2006-08-15 14:22:35 +0200242#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese899620c2006-08-15 14:22:35 +0200244#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
246#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
247#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese899620c2006-08-15 14:22:35 +0200248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_ALT_MEMTEST 1 /* Enable more extensive memtest*/
250#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
251#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roese899620c2006-08-15 14:22:35 +0200252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
254#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roese899620c2006-08-15 14:22:35 +0200255
Stefan Roese5bc528f2006-10-07 11:35:25 +0200256#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Stefan Roese899620c2006-08-15 14:22:35 +0200257#define CONFIG_LOOPW 1 /* enable loopw command */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200258#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Stefan Roese899620c2006-08-15 14:22:35 +0200259#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100260#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
261
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
Stefan Roese899620c2006-08-15 14:22:35 +0200263
Stefan Roese899620c2006-08-15 14:22:35 +0200264/*-----------------------------------------------------------------------
265 * PCI stuff
266 *-----------------------------------------------------------------------
267 */
268/* General PCI */
269#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000270#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese899620c2006-08-15 14:22:35 +0200271#define CONFIG_PCI_PNP /* do pci plug-and-play */
272#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
Stefan Roese1c2ce222006-11-27 14:12:17 +0100274#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
Stefan Roese899620c2006-08-15 14:22:35 +0200275
276/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
278#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese899620c2006-08-15 14:22:35 +0200279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
281#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Stefan Roese899620c2006-08-15 14:22:35 +0200282
283/*-----------------------------------------------------------------------
284 * FPGA stuff
Stefan Roese1c2ce222006-11-27 14:12:17 +0100285 *-----------------------------------------------------------------------*/
Matthias Fuchs01335022007-12-27 17:12:34 +0100286#define CONFIG_FPGA
287#define CONFIG_FPGA_ALTERA
288#define CONFIG_FPGA_CYCLON2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_FPGA_CHECK_CTRLC
290#define CONFIG_SYS_FPGA_PROG_FEEDBACK
Stefan Roese899620c2006-08-15 14:22:35 +0200291#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
292 Reihe geschaltet -> sollte gehen,
293 aufpassen mit Datasize ist jetzt
294 halt doppelt so gross ... Seite 306
295 ist das mit den multiple Device in PS
296 Mode erklaert ...*/
297
Stefan Roese899620c2006-08-15 14:22:35 +0200298/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
300#define CONFIG_SYS_GPIO_DATA 19 /* FPGA data pin (cpu output) */
301#define CONFIG_SYS_GPIO_STATUS 20 /* FPGA status pin (cpu input) */
302#define CONFIG_SYS_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */
303#define CONFIG_SYS_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */
Stefan Roese899620c2006-08-15 14:22:35 +0200304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_GPIO_SEL_DPR 14 /* cpu output */
306#define CONFIG_SYS_GPIO_SEL_AVR 15 /* cpu output */
307#define CONFIG_SYS_GPIO_PROG_EN 23 /* cpu output */
Stefan Roese899620c2006-08-15 14:22:35 +0200308
Stefan Roese1c2ce222006-11-27 14:12:17 +0100309/*-----------------------------------------------------------------------
310 * Definitions for GPIO setup
311 *-----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_GPIO_SHUTDOWN (0x80000000 >> 6)
313#define CONFIG_SYS_GPIO_SSD_EMPTY (0x80000000 >> 9)
314#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 26)
315#define CONFIG_SYS_GPIO_REV0 (0x80000000 >> 14)
316#define CONFIG_SYS_GPIO_REV1 (0x80000000 >> 15)
Stefan Roese1c2ce222006-11-27 14:12:17 +0100317
318/*-----------------------------------------------------------------------
Stefan Roese899620c2006-08-15 14:22:35 +0200319 * NAND-FLASH stuff
Stefan Roese1c2ce222006-11-27 14:12:17 +0100320 *-----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_MAX_NAND_DEVICE 4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
323#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \
324 CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
325#define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */
Prabhakar Kushwaha68ec9c82013-10-04 13:47:58 +0530326#define CONFIG_SYS_NAND_MAX_OOBFREE 2
327#define CONFIG_SYS_NAND_MAX_ECCPOS 56
Stefan Roese899620c2006-08-15 14:22:35 +0200328
329/*-----------------------------------------------------------------------
330 * External Bus Controller (EBC) Setup
331 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
Stefan Roese899620c2006-08-15 14:22:35 +0200333
334/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_EBC_PB0AP 0x92015480
336#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
Stefan Roese899620c2006-08-15 14:22:35 +0200337
Stefan Roese5bc528f2006-10-07 11:35:25 +0200338/* Memory Bank 1 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_EBC_PB1AP 0x01840380 /* TWT=3 */
340#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
Stefan Roese899620c2006-08-15 14:22:35 +0200341
342/*
343 * For booting Linux, the board info and command line data
344 * have to be in the first 8 MB of memory, since this is
345 * the maximum mapped by the Linux kernel during initialization.
346 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese899620c2006-08-15 14:22:35 +0200348
Jon Loeliger0b361c92007-07-04 22:31:42 -0500349#if defined(CONFIG_CMD_KGDB)
Stefan Roese899620c2006-08-15 14:22:35 +0200350#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Stefan Roese899620c2006-08-15 14:22:35 +0200351#endif
Stefan Roese94627322008-03-19 10:23:43 +0100352
353/* pass open firmware flat tree */
354#define CONFIG_OF_LIBFDT 1
355#define CONFIG_OF_BOARD_SETUP 1
356
Stefan Roese899620c2006-08-15 14:22:35 +0200357#endif /* __CONFIG_H */