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Ulf Samuelssoncb82a532009-03-27 23:26:43 +01001/*
Andreas Bießmann99fa97e2010-10-18 22:58:29 +02002 * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
3 *
4 * based on previous work by
5 *
Ulf Samuelssoncb82a532009-03-27 23:26:43 +01006 * Ulf Samuelsson <ulf@atmel.com>
7 * Rick Bronson <rick@efn.org>
8 *
9 * Configuration settings for the AT91RM9200EK board.
10 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010012 */
13
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020014#ifndef __AT91RM9200EK_CONFIG_H__
15#define __AT91RM9200EK_CONFIG_H__
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010016
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020017#include <asm/sizes.h>
Jens Scharsig425de622010-02-03 22:45:42 +010018
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010019/*
Andreas Bießmann3a4ff8b2010-11-30 09:45:03 +000020 * set some initial configurations depending on configure target
21 *
22 * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0
23 * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
24 * initialisation was done by some preloader
25 */
26#ifdef CONFIG_RAMBOOT
27#define CONFIG_SKIP_LOWLEVEL_INIT
28#define CONFIG_SYS_TEXT_BASE 0x20100000
29#else
30#define CONFIG_SYS_TEXT_BASE 0x10000000
31#endif
32
33/*
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020034 * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
35 * AT91C_MAIN_CLOCK is the frequency of PLLA output
36 * AT91C_MASTER_CLOCK is the peripherial clock
37 * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
38 * set in arch/arm/cpu/arm920t/at91/timer.c)
39 * CONFIG_SYS_HZ is the tick rate for timer tc0
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010040 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020041#define AT91C_XTAL_CLOCK 18432000
Andreas Bießmann6a372e92011-06-12 01:49:12 +000042#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020043#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
44#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
45#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020046
47/* CPU configuration */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020048#define CONFIG_AT91RM9200
49#define CONFIG_AT91RM9200EK
50#define CONFIG_CPUAT91
51#define USE_920T_MMU
52
Andreas Bießmann6a372e92011-06-12 01:49:12 +000053#include <asm/hardware.h> /* needed for port definitions */
54
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020055#define CONFIG_CMDLINE_TAG
56#define CONFIG_SETUP_MEMORY_TAGS
57#define CONFIG_INITRD_TAG
58
Andreas Bießmann3432a932011-06-12 01:49:14 +000059#define CONFIG_BOARD_EARLY_INIT_F
60
Nicolas Ferref9129fe2013-02-20 00:16:24 +000061#define CONFIG_CMD_BOOTZ
Nicolas Ferre36873e72013-02-20 00:16:23 +000062#define CONFIG_OF_LIBFDT
63
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010064/*
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020065 * Memory Configuration
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010066 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020067#define CONFIG_NR_DRAM_BANKS 1
68#define CONFIG_SYS_SDRAM_BASE 0x20000000
69#define CONFIG_SYS_SDRAM_SIZE SZ_32M
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010070
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020071#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
72#define CONFIG_SYS_MEMTEST_END \
73 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010074
75/*
76 * LowLevel Init
77 */
78#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020079#define CONFIG_SYS_USE_MAIN_OSCILLATOR
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010080/* flash */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010081#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
82#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
83
84/* clocks */
85#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
86#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
87/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
88#define CONFIG_SYS_MCKR_VAL 0x00000202
89
90/* sdram */
91#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
92#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
93#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
94#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
95#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020096#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
Andreas Bießmann066df1a2010-12-04 11:31:46 +000097#define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010098#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
99#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
100#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
101#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
102#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
103#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100104#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
105
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100106/*
107 * Hardware drivers
108 */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100109/*
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200110 * Choose a USART for serial console
111 * CONFIG_DBGU is DBGU unit on J10
112 * CONFIG_USART1 is USART1 on J14
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100113 */
Andreas Bießmann3432a932011-06-12 01:49:14 +0000114#define CONFIG_ATMEL_USART
115#define CONFIG_USART_BASE ATMEL_BASE_DBGU
116#define CONFIG_USART_ID 0/* ignored in arm */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100117
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100118#define CONFIG_BAUDRATE 115200
119
120/*
121 * Command line configuration.
122 */
123#include <config_cmd_default.h>
124
125#define CONFIG_CMD_DHCP
126#define CONFIG_CMD_FAT
127#define CONFIG_CMD_MII
128#define CONFIG_CMD_PING
Andreas Bießmann3b835222010-10-18 22:58:31 +0200129#define CONFIG_CMD_USB
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100130#undef CONFIG_CMD_FPGA
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100131
132/*
133 * Network Driver Setting
134 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200135#define CONFIG_DRIVER_AT91EMAC
136#define CONFIG_SYS_RX_ETH_BUFFER 16
137#define CONFIG_RMII
138#define CONFIG_MII
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100139
140/*
141 * NOR Flash
142 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200143#define CONFIG_FLASH_CFI_DRIVER
144#define CONFIG_SYS_FLASH_CFI
145#define CONFIG_SYS_FLASH_BASE 0x10000000
146#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
147#define PHYS_FLASH_SIZE SZ_8M
148#define CONFIG_SYS_MAX_FLASH_BANKS 1
149#define CONFIG_SYS_MAX_FLASH_SECT 256
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100150#define CONFIG_SYS_FLASH_PROTECTION
151
152/*
Andreas Bießmann3b835222010-10-18 22:58:31 +0200153 * USB Config
154 */
155#define CONFIG_USB_ATMEL 1
Bo Shendcd2f1a2013-10-21 16:14:00 +0800156#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Andreas Bießmann3b835222010-10-18 22:58:31 +0200157#define CONFIG_USB_OHCI_NEW 1
158#define CONFIG_USB_KEYBOARD 1
159#define CONFIG_USB_STORAGE 1
160#define CONFIG_DOS_PARTITION 1
161
162#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
Jens Scharsig80733992011-02-19 06:17:02 +0000163#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE
Andreas Bießmann3b835222010-10-18 22:58:31 +0200164#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
165#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
166
167/*
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100168 * Environment Settings
169 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200170#define CONFIG_ENV_IS_IN_FLASH
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100171
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100172/*
173 * after u-boot.bin
174 */
175#define CONFIG_ENV_ADDR \
176 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200177#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100178/* The following #defines are needed to get flash environment right */
179#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200180#define CONFIG_SYS_MONITOR_LEN SZ_256K
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100181
182/*
183 * Boot option
184 */
185#define CONFIG_BOOTDELAY 3
186
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200187/* default load address */
188#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
189#define CONFIG_ENV_OVERWRITE
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100190
191/*
192 * Shell Settings
193 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200194#define CONFIG_CMDLINE_EDITING
195#define CONFIG_SYS_LONGHELP
196#define CONFIG_AUTO_COMPLETE
197#define CONFIG_SYS_HUSH_PARSER
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100198#define CONFIG_SYS_PROMPT "U-Boot> "
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100199#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
200#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
201/* Print Buffer Size */
202#define CONFIG_SYS_PBSIZE \
203 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
204
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100205/*
206 * Size of malloc() pool
207 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200208#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
209 SZ_4K)
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100210
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200211#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200212 - GENERATED_GBL_DATA_SIZE)
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200213
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200214#endif /* __AT91RM9200EK_CONFIG_H__ */