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Stefano Babicf8f8acd2010-07-06 19:32:09 +02001/*
2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
5 *
6 * Configuration settings for the MX51-3Stack Freescale board.
7 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
Stefano Babicf8f8acd2010-07-06 19:32:09 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Stefano Babicf8f8acd2010-07-06 19:32:09 +020014
15#define CONFIG_MX51 /* in a mx51 */
Fabio Estevamc02d8282011-05-10 08:13:56 +000016#define CONFIG_SYS_TEXT_BASE 0x97800000
Stefano Babicf8f8acd2010-07-06 19:32:09 +020017
Liu Hui-R64343595f3e52011-01-03 22:27:35 +000018#include <asm/arch/imx-regs.h>
19
Stefano Babicf8f8acd2010-07-06 19:32:09 +020020#define CONFIG_DISPLAY_CPUINFO
21#define CONFIG_DISPLAY_BOARDINFO
22
23#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020024#define CONFIG_SETUP_MEMORY_TAGS
25#define CONFIG_INITRD_TAG
Helmut Raiger9660e442011-10-20 04:19:47 +000026#define CONFIG_BOARD_LATE_INIT
Stefano Babicf8f8acd2010-07-06 19:32:09 +020027
Stefano Babic1cf820f2011-10-27 14:30:27 +020028#ifndef MACH_TYPE_TTC_VISION2
29#define MACH_TYPE_TTC_VISION2 2775
30#endif
Fabio Estevamdb545e42011-09-23 02:50:51 +000031#define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
32
Stefano Babicf8f8acd2010-07-06 19:32:09 +020033/*
34 * Size of malloc() pool
35 */
Stefano Babice9934f02011-09-28 11:21:15 +020036#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Stefano Babicf8f8acd2010-07-06 19:32:09 +020037
Stefano Babicf8f8acd2010-07-06 19:32:09 +020038/*
39 * Hardware drivers
40 */
41#define CONFIG_MXC_UART
Stefano Babic40f6fff2011-11-22 15:22:39 +010042#define CONFIG_MXC_UART_BASE UART3_BASE
Stefano Babicf8f8acd2010-07-06 19:32:09 +020043#define CONFIG_MXC_GPIO
44#define CONFIG_MXC_SPI
45#define CONFIG_HW_WATCHDOG
46
47 /*
48 * SPI Configs
49 * */
50#define CONFIG_FSL_SF
51#define CONFIG_CMD_SF
52
53#define CONFIG_SPI_FLASH
54#define CONFIG_SPI_FLASH_STMICRO
55
56/*
57 * Use gpio 4 pin 25 as chip select for SPI flash
58 * This corresponds to gpio 121
59 */
Fabio Estevam94f00032012-03-22 14:29:04 +000060#define CONFIG_SF_DEFAULT_CS (1 | (121 << 8))
Stefano Babicf8f8acd2010-07-06 19:32:09 +020061#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
62#define CONFIG_SF_DEFAULT_SPEED 25000000
63
64#define CONFIG_ENV_SPI_CS (1 | (121 << 8))
65#define CONFIG_ENV_SPI_BUS 0
66#define CONFIG_ENV_SPI_MAX_HZ 25000000
67#define CONFIG_ENV_SPI_MODE SPI_MODE_0
68
69#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
70#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
71#define CONFIG_ENV_SIZE (4 * 1024)
72
73#define CONFIG_FSL_ENV_IN_SF
74#define CONFIG_ENV_IS_IN_SPI_FLASH
75
76/* PMIC Controller */
Łukasz Majewskibe3b51a2012-11-13 03:22:14 +000077#define CONFIG_POWER
78#define CONFIG_POWER_SPI
79#define CONFIG_POWER_FSL
Stefano Babicf8f8acd2010-07-06 19:32:09 +020080#define CONFIG_FSL_PMIC_BUS 0
81#define CONFIG_FSL_PMIC_CS 0
82#define CONFIG_FSL_PMIC_CLK 2500000
83#define CONFIG_FSL_PMIC_MODE SPI_MODE_0
Stefano Babicbac395e2011-10-02 12:58:03 +020084#define CONFIG_FSL_PMIC_BITLEN 32
Fabio Estevam4e8b7542011-10-24 06:44:15 +000085#define CONFIG_RTC_MC13XXX
Stefano Babicf8f8acd2010-07-06 19:32:09 +020086
87/*
88 * MMC Configs
89 */
90#define CONFIG_FSL_ESDHC
91#ifdef CONFIG_FSL_ESDHC
92#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
93#define CONFIG_SYS_FSL_ESDHC_NUM 1
94
95#define CONFIG_MMC
96
97#define CONFIG_CMD_MMC
98#define CONFIG_GENERIC_MMC
99#define CONFIG_CMD_FAT
100#define CONFIG_DOS_PARTITION
101#endif
102
103#define CONFIG_CMD_DATE
104
105/*
106 * Eth Configs
107 */
108#define CONFIG_HAS_ETH1
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200109#define CONFIG_MII
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200110
111#define CONFIG_FEC_MXC
112#define IMX_FEC_BASE FEC_BASE_ADDR
113#define CONFIG_FEC_MXC_PHYADDR 0x1F
114
115#define CONFIG_CMD_PING
116#define CONFIG_CMD_MII
117#define CONFIG_CMD_NET
118
119/* allow to overwrite serial and ethaddr */
120#define CONFIG_ENV_OVERWRITE
121#define CONFIG_CONS_INDEX 3
122#define CONFIG_BAUDRATE 115200
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200123
124/***********************************************************
125 * Command definition
126 ***********************************************************/
127
128#include <config_cmd_default.h>
129
130#define CONFIG_CMD_SPI
131#undef CONFIG_CMD_IMLS
132
133#define CONFIG_BOOTDELAY 3
134
135#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
136
137#define CONFIG_EXTRA_ENV_SETTINGS \
138 "netdev=eth0\0" \
139 "loadaddr=0x90800000\0"
140
141/*
142 * Miscellaneous configurable options
143 */
144#define CONFIG_SYS_LONGHELP
145#define CONFIG_SYS_PROMPT "Vision II U-boot > "
146#define CONFIG_AUTO_COMPLETE
147#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
148
149/* Print Buffer Size */
150#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
151 sizeof(CONFIG_SYS_PROMPT) + 16)
152#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
153#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
154
155#define CONFIG_SYS_MEMTEST_START 0x90000000
156#define CONFIG_SYS_MEMTEST_END 0x10000
157
158#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
159
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200160#define CONFIG_CMDLINE_EDITING
161#define CONFIG_SYS_HUSH_PARSER
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200162
163/*
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200164 * Physical Memory Map
165 */
166#define CONFIG_NR_DRAM_BANKS 2
167#define PHYS_SDRAM_1 CSD0_BASE_ADDR
168#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
169#define PHYS_SDRAM_2 CSD1_BASE_ADDR
170#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
Stefano Babic43883dc2011-01-21 17:39:03 +0100171#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
172#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
173#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200174
Stefano Babic43883dc2011-01-21 17:39:03 +0100175#define CONFIG_SYS_INIT_SP_OFFSET \
176 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
177#define CONFIG_SYS_INIT_SP_ADDR \
178 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
179
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200180#define CONFIG_BOARD_EARLY_INIT_F
181
182/* 166 MHz DDR RAM */
183#define CONFIG_SYS_DDR_CLKSEL 0
184#define CONFIG_SYS_CLKTL_CBCDR 0x19239100
Benoît Thébaudeau39e85762012-11-05 10:07:04 +0000185#define CONFIG_SYS_MAIN_PWR_ON
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200186
187#define CONFIG_SYS_NO_FLASH
188
Stefano Babica0152c42010-10-21 10:34:39 +0200189/*
190 * Framebuffer and LCD
191 */
192#define CONFIG_PREBOOT
Stefano Babice9934f02011-09-28 11:21:15 +0200193#define CONFIG_VIDEO
Fabio Estevam695af9a2012-05-31 07:23:56 +0000194#define CONFIG_VIDEO_IPUV3
Stefano Babice9934f02011-09-28 11:21:15 +0200195#define CONFIG_CFB_CONSOLE
196#define CONFIG_VGA_AS_SINGLE_DEVICE
Fabio Estevamfca37fc2012-08-05 07:31:34 +0000197#define CONFIG_SYS_CONSOLE_IS_IN_ENV
198#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
Stefano Babice9934f02011-09-28 11:21:15 +0200199#define CONFIG_VIDEO_BMP_RLE8
Stefano Babica0152c42010-10-21 10:34:39 +0200200#define CONFIG_SPLASH_SCREEN
201#define CONFIG_CMD_BMP
202#define CONFIG_BMP_16BPP
Fabio Estevam9fbdb1a2012-05-31 07:24:00 +0000203#define CONFIG_IPUV3_CLK 133000000
Stefano Babica0152c42010-10-21 10:34:39 +0200204
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200205#endif /* __CONFIG_H */