Albert ARIBAUD | 7202e8a | 2012-11-26 11:27:37 +0000 | [diff] [blame] | 1 | # |
| 2 | # Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net> |
| 3 | # |
| 4 | # Based on netspace_v2 kwbimage.cfg: |
| 5 | # Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> |
| 6 | # |
| 7 | # Based on Kirkwood support: |
| 8 | # (C) Copyright 2009 |
| 9 | # Marvell Semiconductor <www.marvell.com> |
| 10 | # Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
| 11 | # |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 12 | # SPDX-License-Identifier: GPL-2.0+ |
Albert ARIBAUD | 7202e8a | 2012-11-26 11:27:37 +0000 | [diff] [blame] | 13 | # |
Anatolij Gustschin | b1e6c4c | 2013-04-30 11:15:33 +0000 | [diff] [blame] | 14 | # Refer doc/README.kwbimage for more details about how-to configure |
Albert ARIBAUD | 7202e8a | 2012-11-26 11:27:37 +0000 | [diff] [blame] | 15 | # and create kirkwood boot image |
| 16 | # |
| 17 | |
| 18 | # Boot Media configurations |
| 19 | BOOT_FROM nand # Boot from NAND flash |
| 20 | NAND_PAGE_SIZE 800 |
| 21 | |
| 22 | # SOC registers configuration using bootrom header extension |
| 23 | # Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
| 24 | |
| 25 | # Values taken from image original LaCie U-Boot header dump! |
| 26 | |
| 27 | # Configure RGMII-0 interface pad voltage to 1.8V |
| 28 | DATA 0xFFD100e0 0x1B1B1B9B |
| 29 | |
| 30 | #Dram initalization for SINGLE x16 CL=5 @ 400MHz |
| 31 | DATA 0xFFD01400 0x43000c30 # DDR Configuration register |
| 32 | |
| 33 | DATA 0xFFD01404 0x37743000 # DDR Controller Control Low |
| 34 | |
| 35 | DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) |
| 36 | |
| 37 | DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) |
| 38 | |
| 39 | DATA 0xFFD01410 0x0000CCCC # DDR Address Control |
| 40 | |
| 41 | DATA 0xFFD01414 0x00000000 # DDR Open Pages Control |
| 42 | |
| 43 | DATA 0xFFD01418 0x00000000 # DDR Operation |
| 44 | |
| 45 | DATA 0xFFD0141C 0x00000662 # DDR Mode |
| 46 | |
| 47 | DATA 0xFFD01420 0x00000004 # DDR Extended Mode |
| 48 | |
| 49 | DATA 0xFFD01424 0x0000F07F # DDR Controller Control High |
| 50 | |
| 51 | DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) |
| 52 | |
| 53 | DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) |
| 54 | |
| 55 | DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size |
| 56 | DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 |
| 57 | DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled |
| 58 | DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled |
| 59 | DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled |
| 60 | DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) |
| 61 | DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) |
| 62 | DATA 0xFFD0149C 0x0000E40F # CPU ODT Control |
| 63 | DATA 0xFFD01480 0x00000001 # DDR Initialization Control |
| 64 | DATA 0xFFD20134 0x66666666 |
| 65 | DATA 0xFFD20138 0x66666666 |
| 66 | DATA 0xFFD10000 0x01112222 |
| 67 | DATA 0xFFD1000C 0x00000000 |
| 68 | DATA 0xFFD10104 0x00000000 |
| 69 | DATA 0xFFD10100 0x40000000 |
| 70 | # End of Header extension |
| 71 | DATA 0x0 0x0 |