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Albert ARIBAUD7202e8a2012-11-26 11:27:37 +00001#
2# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
3#
4# Based on netspace_v2 kwbimage.cfg:
5# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
6#
7# Based on Kirkwood support:
8# (C) Copyright 2009
9# Marvell Semiconductor <www.marvell.com>
10# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
11#
Wolfgang Denk1a459662013-07-08 09:37:19 +020012# SPDX-License-Identifier: GPL-2.0+
Albert ARIBAUD7202e8a2012-11-26 11:27:37 +000013#
Anatolij Gustschinb1e6c4c2013-04-30 11:15:33 +000014# Refer doc/README.kwbimage for more details about how-to configure
Albert ARIBAUD7202e8a2012-11-26 11:27:37 +000015# and create kirkwood boot image
16#
17
18# Boot Media configurations
19BOOT_FROM nand # Boot from NAND flash
20NAND_PAGE_SIZE 800
21
22# SOC registers configuration using bootrom header extension
23# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
24
25# Values taken from image original LaCie U-Boot header dump!
26
27# Configure RGMII-0 interface pad voltage to 1.8V
28DATA 0xFFD100e0 0x1B1B1B9B
29
30#Dram initalization for SINGLE x16 CL=5 @ 400MHz
31DATA 0xFFD01400 0x43000c30 # DDR Configuration register
32
33DATA 0xFFD01404 0x37743000 # DDR Controller Control Low
34
35DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
36
37DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
38
39DATA 0xFFD01410 0x0000CCCC # DDR Address Control
40
41DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
42
43DATA 0xFFD01418 0x00000000 # DDR Operation
44
45DATA 0xFFD0141C 0x00000662 # DDR Mode
46
47DATA 0xFFD01420 0x00000004 # DDR Extended Mode
48
49DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
50
51DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
52
53DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
54
55DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
56DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0
57DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
58DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
59DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
60DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
61DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
62DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
63DATA 0xFFD01480 0x00000001 # DDR Initialization Control
64DATA 0xFFD20134 0x66666666
65DATA 0xFFD20138 0x66666666
66DATA 0xFFD10000 0x01112222
67DATA 0xFFD1000C 0x00000000
68DATA 0xFFD10104 0x00000000
69DATA 0xFFD10100 0x40000000
70# End of Header extension
71DATA 0x0 0x0