Paul Barker | 1d49b8d | 2022-04-11 15:41:59 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
| 4 | */ |
| 5 | |
| 6 | #include <dt-bindings/display/tda998x.h> |
| 7 | #include <dt-bindings/interrupt-controller/irq.h> |
| 8 | |
| 9 | &am33xx_pinmux { |
| 10 | nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { |
| 11 | pinctrl-single,pins = < |
| 12 | AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) |
| 13 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) |
| 14 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) |
| 15 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) |
| 16 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) |
| 17 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) |
| 18 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) |
| 19 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) |
| 20 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) |
| 21 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) |
| 22 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) |
| 23 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) |
| 24 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) |
| 25 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) |
| 26 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) |
| 27 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) |
| 28 | AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) |
| 29 | AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 30 | AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 31 | AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 32 | AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 33 | >; |
| 34 | }; |
| 35 | |
| 36 | nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { |
| 37 | pinctrl-single,pins = < |
| 38 | AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) |
| 39 | >; |
| 40 | }; |
| 41 | |
| 42 | mcasp0_pins: mcasp0_pins { |
| 43 | pinctrl-single,pins = < |
| 44 | AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ |
| 45 | AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ |
| 46 | AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) |
| 47 | AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) |
| 48 | AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ |
| 49 | >; |
| 50 | }; |
| 51 | }; |
| 52 | |
| 53 | &lcdc { |
| 54 | status = "okay"; |
| 55 | |
| 56 | /* If you want to get 24 bit RGB and 16 BGR mode instead of |
| 57 | * current 16 bit RGB and 24 BGR modes, set the propety |
| 58 | * below to "crossed" and uncomment the video-ports -property |
| 59 | * in tda19988 node. |
| 60 | */ |
| 61 | blue-and-red-wiring = "straight"; |
| 62 | |
| 63 | port { |
| 64 | lcdc_0: endpoint@0 { |
| 65 | remote-endpoint = <&hdmi_0>; |
| 66 | }; |
| 67 | }; |
| 68 | }; |
| 69 | |
| 70 | &i2c0 { |
| 71 | tda19988: tda19988@70 { |
| 72 | compatible = "nxp,tda998x"; |
| 73 | reg = <0x70>; |
| 74 | nxp,calib-gpios = <&gpio1 25 0>; |
| 75 | interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>; |
| 76 | |
| 77 | pinctrl-names = "default", "off"; |
| 78 | pinctrl-0 = <&nxp_hdmi_bonelt_pins>; |
| 79 | pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; |
| 80 | |
| 81 | /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ |
| 82 | /* video-ports = <0x234501>; */ |
| 83 | |
| 84 | #sound-dai-cells = <0>; |
| 85 | audio-ports = < TDA998x_I2S 0x03>; |
| 86 | |
| 87 | ports { |
Andrew Davis | 211b3d7 | 2023-04-11 13:25:05 -0500 | [diff] [blame] | 88 | #address-cells = <1>; |
| 89 | #size-cells = <0>; |
| 90 | |
Paul Barker | 1d49b8d | 2022-04-11 15:41:59 +0000 | [diff] [blame] | 91 | port@0 { |
Andrew Davis | 211b3d7 | 2023-04-11 13:25:05 -0500 | [diff] [blame] | 92 | reg = <0>; |
| 93 | |
| 94 | hdmi_0: endpoint { |
Paul Barker | 1d49b8d | 2022-04-11 15:41:59 +0000 | [diff] [blame] | 95 | remote-endpoint = <&lcdc_0>; |
| 96 | }; |
| 97 | }; |
| 98 | }; |
| 99 | }; |
| 100 | }; |
| 101 | |
| 102 | &mcasp0 { |
| 103 | #sound-dai-cells = <0>; |
| 104 | pinctrl-names = "default"; |
| 105 | pinctrl-0 = <&mcasp0_pins>; |
| 106 | status = "okay"; |
| 107 | op-mode = <0>; /* MCASP_IIS_MODE */ |
| 108 | tdm-slots = <2>; |
| 109 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
| 110 | 0 0 1 0 |
| 111 | >; |
| 112 | tx-num-evt = <32>; |
| 113 | rx-num-evt = <32>; |
| 114 | }; |
| 115 | |
| 116 | / { |
| 117 | clk_mcasp0_fixed: clk_mcasp0_fixed { |
| 118 | #clock-cells = <0>; |
| 119 | compatible = "fixed-clock"; |
| 120 | clock-frequency = <24576000>; |
| 121 | }; |
| 122 | |
| 123 | clk_mcasp0: clk_mcasp0 { |
| 124 | #clock-cells = <0>; |
| 125 | compatible = "gpio-gate-clock"; |
| 126 | clocks = <&clk_mcasp0_fixed>; |
| 127 | enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ |
| 128 | }; |
| 129 | |
| 130 | sound { |
| 131 | compatible = "simple-audio-card"; |
| 132 | simple-audio-card,name = "TI BeagleBone Black"; |
| 133 | simple-audio-card,format = "i2s"; |
| 134 | simple-audio-card,bitclock-master = <&dailink0_master>; |
| 135 | simple-audio-card,frame-master = <&dailink0_master>; |
| 136 | |
| 137 | dailink0_master: simple-audio-card,cpu { |
| 138 | sound-dai = <&mcasp0>; |
| 139 | clocks = <&clk_mcasp0>; |
| 140 | }; |
| 141 | |
| 142 | simple-audio-card,codec { |
| 143 | sound-dai = <&tda19988>; |
| 144 | }; |
| 145 | }; |
| 146 | }; |