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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 4a463a190f0847edfd1c2880203330ebaf854e2f / . / arch / arm / dts / at91-sama5d2_icp-u-boot.dtsi
blob: cd8976f7e1d5717a0d09eef8bf47cecf3e37e94b [file] [log] [blame]
Eugen Hristevf0854522018-07-06 11:15:10 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * at91-sama5d2_icp-for-uboot.dtsi - Device Tree file for SAMA5D2 ICP board
4 * SAMA5D2 Industrial Connectivity Platform
5 *
6 * Copyright (c) 2019, Microchip Technology Inc. and its subsidiaries
7 * 2019, Eugen Hristev <eugen.hristev@microchip.com>
8 */
9
10/ {
11 chosen {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]12 bootph-all;
Eugen Hristevf0854522018-07-06 11:15:10 +0300[diff] [blame]13 };
14};
15
Eugen Hristevf0854522018-07-06 11:15:10 +0300[diff] [blame]16&pinctrl_mikrobus1_uart {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]17 bootph-all;
Eugen Hristevf0854522018-07-06 11:15:10 +0300[diff] [blame]18};
Mihai Sain5b435082021-08-17 13:29:22 +0300[diff] [blame]19
20&pinctrl_qspi1_sck_cs_default {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]21 bootph-all;
Mihai Sain5b435082021-08-17 13:29:22 +0300[diff] [blame]22};
23
24&pinctrl_qspi1_dat_default {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]25 bootph-all;
Mihai Sain5b435082021-08-17 13:29:22 +0300[diff] [blame]26};
27
Eugen Hristevb6a8cce2021-08-17 13:29:23 +0300[diff] [blame]28&pinctrl_sdmmc0_default {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]29 bootph-all;
Eugen Hristevb6a8cce2021-08-17 13:29:23 +0300[diff] [blame]30};
31
Mihai Sain5b435082021-08-17 13:29:22 +0300[diff] [blame]32&qspi1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]33 bootph-all;
Mihai Sain5b435082021-08-17 13:29:22 +0300[diff] [blame]34
35 flash@0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]36 bootph-all;
Mihai Sain5b435082021-08-17 13:29:22 +0300[diff] [blame]37 };
38};
Eugen Hristevb6a8cce2021-08-17 13:29:23 +0300[diff] [blame]39
40&sdmmc0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]41 bootph-all;
Eugen Hristevb6a8cce2021-08-17 13:29:23 +0300[diff] [blame]42};
43
44&uart0 { /* mikrobus1 uart */
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]45 bootph-all;
Eugen Hristevb6a8cce2021-08-17 13:29:23 +0300[diff] [blame]46};
47