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Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +05307 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <usb.h>
12#include "ehci.h"
Stefan Roesefe11ae22015-06-29 14:58:15 +020013#include <linux/mbus.h>
Lei Wena7efd712011-10-18 20:11:42 +053014#include <asm/arch/cpu.h>
Stefan Roesecd482252015-09-01 11:39:44 +020015#include <dm.h>
Albert ARIBAUD805ad7e2012-01-15 22:08:40 +000016
17#if defined(CONFIG_KIRKWOOD)
Stefan Roese3dc23f72014-10-22 12:13:06 +020018#include <asm/arch/soc.h>
Albert ARIBAUD805ad7e2012-01-15 22:08:40 +000019#elif defined(CONFIG_ORION5X)
20#include <asm/arch/orion5x.h>
21#endif
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +053022
Albert ARIBAUD74d34422012-01-15 22:08:39 +000023DECLARE_GLOBAL_DATA_PTR;
24
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +053025#define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
26#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
27#define USB_TARGET_DRAM 0x0
28
Stefan Roesec6cfcc92016-07-18 17:24:56 +020029#define USB2_SBUSCFG_OFF 0x90
30
31#define USB_SBUSCFG_BAWR_OFF 0x6
32#define USB_SBUSCFG_BARD_OFF 0x3
33#define USB_SBUSCFG_AHBBRST_OFF 0x0
34
35#define USB_SBUSCFG_BAWR_ALIGN_64B 0x4
36#define USB_SBUSCFG_BARD_ALIGN_64B 0x4
37#define USB_SBUSCFG_AHBBRST_INCR16 0x7
38
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +053039/*
40 * USB 2.0 Bridge Address Decoding registers setup
41 */
Stefan Roesecd482252015-09-01 11:39:44 +020042#ifdef CONFIG_DM_USB
Stefan Roesefe11ae22015-06-29 14:58:15 +020043
Stefan Roesecd482252015-09-01 11:39:44 +020044struct ehci_mvebu_priv {
45 struct ehci_ctrl ehci;
46 fdt_addr_t hcd_base;
47};
Stefan Roesefe11ae22015-06-29 14:58:15 +020048
49/*
50 * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
51 * to the common mvebu archticture including the mbus setup, this
52 * will be the only function needed to configure the access windows
53 */
Stefan Roesec6cfcc92016-07-18 17:24:56 +020054static void usb_brg_adrdec_setup(void *base)
Stefan Roesefe11ae22015-06-29 14:58:15 +020055{
56 const struct mbus_dram_target_info *dram;
57 int i;
58
59 dram = mvebu_mbus_dram_info();
60
61 for (i = 0; i < 4; i++) {
Stefan Roesecd482252015-09-01 11:39:44 +020062 writel(0, base + USB_WINDOW_CTRL(i));
63 writel(0, base + USB_WINDOW_BASE(i));
Stefan Roesefe11ae22015-06-29 14:58:15 +020064 }
65
66 for (i = 0; i < dram->num_cs; i++) {
67 const struct mbus_dram_window *cs = dram->cs + i;
68
69 /* Write size, attributes and target id to control register */
Stefan Roese82b91432015-07-22 10:01:30 +020070 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
71 (dram->mbus_dram_target_id << 4) | 1,
Stefan Roesecd482252015-09-01 11:39:44 +020072 base + USB_WINDOW_CTRL(i));
Stefan Roesefe11ae22015-06-29 14:58:15 +020073
74 /* Write base address to base register */
Stefan Roesecd482252015-09-01 11:39:44 +020075 writel(cs->base, base + USB_WINDOW_BASE(i));
Stefan Roesefe11ae22015-06-29 14:58:15 +020076 }
77}
Stefan Roesecd482252015-09-01 11:39:44 +020078
Stefan Roesec6cfcc92016-07-18 17:24:56 +020079static void marvell_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
80 uint32_t *status_reg, uint32_t *reg)
81{
82 struct ehci_mvebu_priv *priv = ctrl->priv;
83
84 /*
85 * Set default value for reg SBUSCFG, which is Control for the AMBA
86 * system bus interface:
87 * BAWR = BARD = 4 : Align rd/wr bursts packets larger than 64 bytes
88 * AHBBRST = 7 : Align AHB burst for packets larger than 64 bytes
89 */
90 writel((USB_SBUSCFG_BAWR_ALIGN_64B << USB_SBUSCFG_BAWR_OFF) |
91 (USB_SBUSCFG_BARD_ALIGN_64B << USB_SBUSCFG_BARD_OFF) |
92 (USB_SBUSCFG_AHBBRST_INCR16 << USB_SBUSCFG_AHBBRST_OFF),
93 priv->hcd_base + USB2_SBUSCFG_OFF);
94
95 mdelay(50);
96}
97
98static struct ehci_ops marvell_ehci_ops = {
99 .powerup_fixup = NULL,
100};
101
Stefan Roesecd482252015-09-01 11:39:44 +0200102static int ehci_mvebu_probe(struct udevice *dev)
103{
104 struct ehci_mvebu_priv *priv = dev_get_priv(dev);
105 struct ehci_hccr *hccr;
106 struct ehci_hcor *hcor;
107
108 /*
109 * Get the base address for EHCI controller from the device node
110 */
Simon Glassa821c4a2017-05-17 17:18:05 -0600111 priv->hcd_base = devfdt_get_addr(dev);
Stefan Roesecd482252015-09-01 11:39:44 +0200112 if (priv->hcd_base == FDT_ADDR_T_NONE) {
113 debug("Can't get the EHCI register base address\n");
114 return -ENXIO;
115 }
116
Stefan Roesec6cfcc92016-07-18 17:24:56 +0200117 /*
118 * For SoCs without hlock like Armada3700 we need to program the sbuscfg
119 * reg to guarantee AHB master's burst will not overrun or underrun
120 * the FIFO. Otherwise all USB2 write option will fail.
121 * Also, the address decoder doesn't need to get setup with this
122 * SoC, so don't call usb_brg_adrdec_setup().
123 */
Simon Glass911f3ae2017-05-18 20:08:57 -0600124 if (device_is_compatible(dev, "marvell,armada3700-ehci"))
Stefan Roesec6cfcc92016-07-18 17:24:56 +0200125 marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
126 else
127 usb_brg_adrdec_setup((void *)priv->hcd_base);
Stefan Roesecd482252015-09-01 11:39:44 +0200128
129 hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
130 hcor = (struct ehci_hcor *)
Stefan Roesec6cfcc92016-07-18 17:24:56 +0200131 ((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
Stefan Roesecd482252015-09-01 11:39:44 +0200132
Stefan Roesec6cfcc92016-07-18 17:24:56 +0200133 debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
134 (uintptr_t)hccr, (uintptr_t)hcor,
135 (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
Stefan Roesecd482252015-09-01 11:39:44 +0200136
Stefan Roesec6cfcc92016-07-18 17:24:56 +0200137 return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0,
138 USB_INIT_HOST);
Stefan Roesecd482252015-09-01 11:39:44 +0200139}
140
Stefan Roesecd482252015-09-01 11:39:44 +0200141static const struct udevice_id ehci_usb_ids[] = {
142 { .compatible = "marvell,orion-ehci", },
Stefan Roesec6cfcc92016-07-18 17:24:56 +0200143 { .compatible = "marvell,armada3700-ehci", },
Stefan Roesecd482252015-09-01 11:39:44 +0200144 { }
145};
146
147U_BOOT_DRIVER(ehci_mvebu) = {
148 .name = "ehci_mvebu",
149 .id = UCLASS_USB,
150 .of_match = ehci_usb_ids,
151 .probe = ehci_mvebu_probe,
Masahiro Yamada40527342016-09-06 22:17:34 +0900152 .remove = ehci_deregister,
Stefan Roesecd482252015-09-01 11:39:44 +0200153 .ops = &ehci_usb_ops,
154 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
155 .priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv),
156 .flags = DM_FLAG_ALLOC_PRIV_DMA,
157};
158
Stefan Roesefe11ae22015-06-29 14:58:15 +0200159#else
Anton Schubert8a333712015-07-23 15:02:09 +0200160#define MVUSB_BASE(port) MVUSB0_BASE
161
162static void usb_brg_adrdec_setup(int index)
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530163{
164 int i;
Albert ARIBAUD74d34422012-01-15 22:08:39 +0000165 u32 size, base, attrib;
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530166
167 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
168
169 /* Enable DRAM bank */
170 switch (i) {
171 case 0:
Albert ARIBAUD74d34422012-01-15 22:08:39 +0000172 attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530173 break;
174 case 1:
Albert ARIBAUD74d34422012-01-15 22:08:39 +0000175 attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530176 break;
177 case 2:
Albert ARIBAUD74d34422012-01-15 22:08:39 +0000178 attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530179 break;
180 case 3:
Albert ARIBAUD74d34422012-01-15 22:08:39 +0000181 attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530182 break;
183 default:
184 /* invalide bank, disable access */
185 attrib = 0;
186 break;
187 }
188
Albert ARIBAUD74d34422012-01-15 22:08:39 +0000189 size = gd->bd->bi_dram[i].size;
190 base = gd->bd->bi_dram[i].start;
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530191 if ((size) && (attrib))
Stefan Roese82b91432015-07-22 10:01:30 +0200192 writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
193 attrib, MVCPU_WIN_ENABLE),
194 MVUSB0_BASE + USB_WINDOW_CTRL(i));
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530195 else
Stefan Roese82b91432015-07-22 10:01:30 +0200196 writel(MVCPU_WIN_DISABLE,
197 MVUSB0_BASE + USB_WINDOW_CTRL(i));
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530198
Stefan Roese82b91432015-07-22 10:01:30 +0200199 writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530200 }
201}
202
203/*
204 * Create the appropriate control structures to manage
205 * a new EHCI host controller.
206 */
Troy Kisky127efc42013-10-10 15:27:57 -0700207int ehci_hcd_init(int index, enum usb_init_type init,
208 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530209{
Anton Schubert8a333712015-07-23 15:02:09 +0200210 usb_brg_adrdec_setup(index);
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530211
Anton Schubert8a333712015-07-23 15:02:09 +0200212 *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100);
Lucas Stach676ae062012-09-26 00:14:35 +0200213 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
214 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530215
Albert ARIBAUD74d34422012-01-15 22:08:39 +0000216 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
Lucas Stach676ae062012-09-26 00:14:35 +0200217 (uint32_t)*hccr, (uint32_t)*hcor,
218 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530219
220 return 0;
221}
222
223/*
224 * Destroy the appropriate control structures corresponding
225 * the the EHCI host controller.
226 */
Lucas Stach676ae062012-09-26 00:14:35 +0200227int ehci_hcd_stop(int index)
Prafulla Wadaskar1d8937a2009-06-29 20:56:43 +0530228{
229 return 0;
230}
Stefan Roesecd482252015-09-01 11:39:44 +0200231
232#endif /* CONFIG_DM_USB */