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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Rick Chen6020faf2017-12-26 13:55:51 +08002/*
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
Rick Chen6020faf2017-12-26 13:55:51 +08005 */
6
7#ifndef _ASM_RISCV_CACHE_H
8#define _ASM_RISCV_CACHE_H
9
Rick Chen52923c62018-11-07 09:34:06 +080010/* cache */
Zong Li30fa33d2021-09-01 15:01:43 +080011void cache_flush(void);
Rick Chen52923c62018-11-07 09:34:06 +080012
Rick Chen6020faf2017-12-26 13:55:51 +080013/*
14 * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
15 * We use that value for aligning DMA buffers unless the board config has
16 * specified an alternate cache line size.
17 */
18#ifdef CONFIG_SYS_CACHELINE_SIZE
19#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
20#else
21#define ARCH_DMA_MINALIGN 32
22#endif
23
24#endif /* _ASM_RISCV_CACHE_H */