| TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * mcf5329.h -- Definitions for Freescale Coldfire 5329 |
| 3 | * |
| 4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #ifndef mcf5235_h |
| 27 | #define mcf5235_h |
| 28 | /****************************************************************************/ |
| 29 | |
| 30 | /********************************************************************* |
| 31 | * System Control Module (SCM) |
| 32 | *********************************************************************/ |
| 33 | |
| 34 | /* Bit definition and macros for SCM_IPSBAR */ |
| 35 | #define SCM_IPSBAR_BA(x) (((x)&0x03)<<30) |
| 36 | #define SCM_IPSBAR_V (0x00000001) |
| 37 | |
| 38 | /* Bit definition and macros for SCM_RAMBAR */ |
| 39 | #define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16) |
| 40 | #define SCM_RAMBAR_BDE (0x00000200) |
| 41 | |
| 42 | /* Bit definition and macros for SCM_CRSR */ |
| 43 | #define SCM_CRSR_EXT (0x80) |
| 44 | |
| 45 | /* Bit definitions and macros for SCM_CWCR */ |
| 46 | #define SCM_CWCR_CWE (0x80) |
| 47 | #define SCM_CWCR_CWRI (0x40) |
| 48 | #define SCM_CWCR_CWT(x) (((x)&0x07)<<3) |
| 49 | #define SCM_CWCR_CWTA (0x04) |
| 50 | #define SCM_CWCR_CWTAVAL (0x02) |
| 51 | #define SCM_CWCR_CWTIC (0x01) |
| 52 | |
| 53 | /* Bit definitions and macros for SCM_LPICR */ |
| 54 | #define SCM_LPICR_ENBSTOP (0x80) |
| 55 | #define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) |
| 56 | #define SCM_LPICR_XLPM_IPL_ANY (0x00) |
| 57 | #define SCM_LPICR_XLPM_IPL_L2_7 (0x10) |
| 58 | #define SCM_LPICR_XLPM_IPL_L3_7 (0x20) |
| 59 | #define SCM_LPICR_XLPM_IPL_L4_7 (0x30) |
| 60 | #define SCM_LPICR_XLPM_IPL_L5_7 (0x40) |
| 61 | #define SCM_LPICR_XLPM_IPL_L6_7 (0x50) |
| 62 | #define SCM_LPICR_XLPM_IPL_L7 (0x70) |
| 63 | |
| 64 | /* Bit definitions and macros for SCM_DMAREQC */ |
| 65 | #define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16) |
| 66 | #define SCM_DMAREQC_EXT_ETPU (0x00080000) |
| 67 | #define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000) |
| 68 | #define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000) |
| 69 | #define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000) |
| 70 | #define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12) |
| 71 | #define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8) |
| 72 | #define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4) |
| 73 | #define SCM_DMAREQC_DMAC0(x) (((x)&0x0F)) |
| 74 | #define SCM_DMAREQC_DMACn_DTMR0 (0x04) |
| 75 | #define SCM_DMAREQC_DMACn_DTMR1 (0x05) |
| 76 | #define SCM_DMAREQC_DMACn_DTMR2 (0x06) |
| 77 | #define SCM_DMAREQC_DMACn_DTMR3 (0x07) |
| 78 | #define SCM_DMAREQC_DMACn_UART0RX (0x08) |
| 79 | #define SCM_DMAREQC_DMACn_UART1RX (0x09) |
| 80 | #define SCM_DMAREQC_DMACn_UART2RX (0x0A) |
| 81 | #define SCM_DMAREQC_DMACn_UART0TX (0x0C) |
| 82 | #define SCM_DMAREQC_DMACn_UART1TX (0x0D) |
| 83 | #define SCM_DMAREQC_DMACn_UART3TX (0x0E) |
| 84 | |
| 85 | /* Bit definitions and macros for SCM_MPARK */ |
| 86 | #define SCM_MPARK_M2_P_EN (0x02000000) |
| 87 | #define SCM_MPARK_M3_PRTY_MSK (0x00C00000) |
| 88 | #define SCM_MPARK_M3_PRTY_4TH (0x00000000) |
| 89 | #define SCM_MPARK_M3_PRTY_3RD (0x00400000) |
| 90 | #define SCM_MPARK_M3_PRTY_2ND (0x00800000) |
| 91 | #define SCM_MPARK_M3_PRTY_1ST (0x00C00000) |
| 92 | #define SCM_MPARK_M2_PRTY_MSK (0x00300000) |
| 93 | #define SCM_MPARK_M2_PRTY_4TH (0x00000000) |
| 94 | #define SCM_MPARK_M2_PRTY_3RD (0x00100000) |
| 95 | #define SCM_MPARK_M2_PRTY_2ND (0x00200000) |
| 96 | #define SCM_MPARK_M2_PRTY_1ST (0x00300000) |
| 97 | #define SCM_MPARK_M0_PRTY_MSK (0x000C0000) |
| 98 | #define SCM_MPARK_M0_PRTY_4TH (0x00000000) |
| 99 | #define SCM_MPARK_M0_PRTY_3RD (0x00040000) |
| 100 | #define SCM_MPARK_M0_PRTY_2ND (0x00080000) |
| 101 | #define SCM_MPARK_M0_PRTY_1ST (0x000C0000) |
| 102 | #define SCM_MPARK_FIXED (0x00004000) |
| 103 | #define SCM_MPARK_TIMEOUT (0x00002000) |
| 104 | #define SCM_MPARK_PRKLAST (0x00001000) |
| 105 | #define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8) |
| 106 | |
| 107 | /* Bit definitions and macros for SCM_MPR */ |
| 108 | #define SCM_MPR_MPR3 (0x08) |
| 109 | #define SCM_MPR_MPR2 (0x04) |
| 110 | #define SCM_MPR_MPR1 (0x02) |
| 111 | #define SCM_MPR_MPR0 (0x01) |
| 112 | |
| 113 | /* Bit definitions and macros for SCM_PACRn */ |
| 114 | #define SCM_PACRn_LOCK1 (0x80) |
| 115 | #define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4) |
| 116 | #define SCM_PACRn_LOCK0 (0x08) |
| 117 | #define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) |
| 118 | |
| 119 | /* Bit definitions and macros for SCM_GPACR */ |
| 120 | #define SCM_PACRn_LOCK (0x80) |
| 121 | #define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07)) |
| 122 | |
| 123 | /********************************************************************* |
| 124 | * SDRAM Controller (SDRAMC) |
| 125 | *********************************************************************/ |
| 126 | /* Bit definitions and macros for SDRAMC_DCR */ |
| 127 | #define SDRAMC_DCR_NAM (0x2000) |
| 128 | #define SDRAMC_DCR_COC (0x1000) |
| 129 | #define SDRAMC_DCR_IS (0x0800) |
| 130 | #define SDRAMC_DCR_RTIM_MASK (0x0C00) |
| 131 | #define SDRAMC_DCR_RTIM_3CLKS (0x0000) |
| 132 | #define SDRAMC_DCR_RTIM_6CLKS (0x0200) |
| 133 | #define SDRAMC_DCR_RTIM_9CLKS (0x0400) |
| 134 | #define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8) |
| 135 | |
| 136 | /* Bit definitions and macros for SDRAMC_DARCn */ |
| 137 | #define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18) |
| 138 | #define SDRAMC_DARCn_RE (0x00008000) |
| 139 | #define SDRAMC_DARCn_CASL_MASK (0x00003000) |
| 140 | #define SDRAMC_DARCn_CASL_C0 (0x00000000) |
| 141 | #define SDRAMC_DARCn_CASL_C1 (0x00001000) |
| 142 | #define SDRAMC_DARCn_CASL_C2 (0x00002000) |
| 143 | #define SDRAMC_DARCn_CASL_C3 (0x00003000) |
| 144 | #define SDRAMC_DARCn_CBM_MASK (0x00000700) |
| 145 | #define SDRAMC_DARCn_CBM_CMD17 (0x00000000) |
| 146 | #define SDRAMC_DARCn_CBM_CMD18 (0x00000100) |
| 147 | #define SDRAMC_DARCn_CBM_CMD19 (0x00000200) |
| 148 | #define SDRAMC_DARCn_CBM_CMD20 (0x00000300) |
| 149 | #define SDRAMC_DARCn_CBM_CMD21 (0x00000400) |
| 150 | #define SDRAMC_DARCn_CBM_CMD22 (0x00000500) |
| 151 | #define SDRAMC_DARCn_CBM_CMD23 (0x00000600) |
| 152 | #define SDRAMC_DARCn_CBM_CMD24 (0x00000700) |
| 153 | #define SDRAMC_DARCn_IMRS (0x00000040) |
| 154 | #define SDRAMC_DARCn_PS_MASK (0x00000030) |
| 155 | #define SDRAMC_DARCn_PS_32 (0x00000000) |
| 156 | #define SDRAMC_DARCn_PS_16 (0x00000010) |
| 157 | #define SDRAMC_DARCn_PS_8 (0x00000020) |
| 158 | #define SDRAMC_DARCn_IP (0x00000008) |
| 159 | |
| 160 | /* Bit definitions and macros for SDRAMC_DMRn */ |
| 161 | #define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18) |
| 162 | #define SDRAMC_DMRn_WP (0x00000100) |
| 163 | #define SDRAMC_DMRn_V (0x00000001) |
| 164 | |
| 165 | /********************************************************************* |
| TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 166 | * Interrupt Controller (INTC) |
| 167 | *********************************************************************/ |
| 168 | #define INT0_LO_RSVD0 (0) |
| 169 | #define INT0_LO_EPORT1 (1) |
| 170 | #define INT0_LO_EPORT2 (2) |
| 171 | #define INT0_LO_EPORT3 (3) |
| 172 | #define INT0_LO_EPORT4 (4) |
| 173 | #define INT0_LO_EPORT5 (5) |
| 174 | #define INT0_LO_EPORT6 (6) |
| 175 | #define INT0_LO_EPORT7 (7) |
| 176 | #define INT0_LO_SCM (8) |
| 177 | #define INT0_LO_DMA0 (9) |
| 178 | #define INT0_LO_DMA1 (10) |
| 179 | #define INT0_LO_DMA2 (11) |
| 180 | #define INT0_LO_DMA3 (12) |
| 181 | #define INT0_LO_UART0 (13) |
| 182 | #define INT0_LO_UART1 (14) |
| 183 | #define INT0_LO_UART2 (15) |
| 184 | #define INT0_LO_RSVD1 (16) |
| 185 | #define INT0_LO_I2C (17) |
| 186 | #define INT0_LO_QSPI (18) |
| 187 | #define INT0_LO_DTMR0 (19) |
| 188 | #define INT0_LO_DTMR1 (20) |
| 189 | #define INT0_LO_DTMR2 (21) |
| 190 | #define INT0_LO_DTMR3 (22) |
| 191 | #define INT0_LO_FEC_TXF (23) |
| 192 | #define INT0_LO_FEC_TXB (24) |
| 193 | #define INT0_LO_FEC_UN (25) |
| 194 | #define INT0_LO_FEC_RL (26) |
| 195 | #define INT0_LO_FEC_RXF (27) |
| 196 | #define INT0_LO_FEC_RXB (28) |
| 197 | #define INT0_LO_FEC_MII (29) |
| 198 | #define INT0_LO_FEC_LC (30) |
| 199 | #define INT0_LO_FEC_HBERR (31) |
| 200 | #define INT0_HI_FEC_GRA (32) |
| 201 | #define INT0_HI_FEC_EBERR (33) |
| 202 | #define INT0_HI_FEC_BABT (34) |
| 203 | #define INT0_HI_FEC_BABR (35) |
| 204 | #define INT0_HI_PIT0 (36) |
| 205 | #define INT0_HI_PIT1 (37) |
| 206 | #define INT0_HI_PIT2 (38) |
| 207 | #define INT0_HI_PIT3 (39) |
| 208 | #define INT0_HI_RNG (40) |
| 209 | #define INT0_HI_SKHA (41) |
| 210 | #define INT0_HI_MDHA (42) |
| 211 | #define INT0_HI_CAN1_BUF0I (43) |
| 212 | #define INT0_HI_CAN1_BUF1I (44) |
| 213 | #define INT0_HI_CAN1_BUF2I (45) |
| 214 | #define INT0_HI_CAN1_BUF3I (46) |
| 215 | #define INT0_HI_CAN1_BUF4I (47) |
| 216 | #define INT0_HI_CAN1_BUF5I (48) |
| 217 | #define INT0_HI_CAN1_BUF6I (49) |
| 218 | #define INT0_HI_CAN1_BUF7I (50) |
| 219 | #define INT0_HI_CAN1_BUF8I (51) |
| 220 | #define INT0_HI_CAN1_BUF9I (52) |
| 221 | #define INT0_HI_CAN1_BUF10I (53) |
| 222 | #define INT0_HI_CAN1_BUF11I (54) |
| 223 | #define INT0_HI_CAN1_BUF12I (55) |
| 224 | #define INT0_HI_CAN1_BUF13I (56) |
| 225 | #define INT0_HI_CAN1_BUF14I (57) |
| 226 | #define INT0_HI_CAN1_BUF15I (58) |
| 227 | #define INT0_HI_CAN1_ERRINT (59) |
| 228 | #define INT0_HI_CAN1_BOFFINT (60) |
| 229 | /* 60-63 Reserved */ |
| 230 | |
| 231 | /* 0 - 7 Reserved */ |
| 232 | #define INT1_LO_CAN1_BUF0I (8) |
| 233 | #define INT1_LO_CAN1_BUF1I (9) |
| 234 | #define INT1_LO_CAN1_BUF2I (10) |
| 235 | #define INT1_LO_CAN1_BUF3I (11) |
| 236 | #define INT1_LO_CAN1_BUF4I (12) |
| 237 | #define INT1_LO_CAN1_BUF5I (13) |
| 238 | #define INT1_LO_CAN1_BUF6I (14) |
| 239 | #define INT1_LO_CAN1_BUF7I (15) |
| 240 | #define INT1_LO_CAN1_BUF8I (16) |
| 241 | #define INT1_LO_CAN1_BUF9I (17) |
| 242 | #define INT1_LO_CAN1_BUF10I (18) |
| 243 | #define INT1_LO_CAN1_BUF11I (19) |
| 244 | #define INT1_LO_CAN1_BUF12I (20) |
| 245 | #define INT1_LO_CAN1_BUF13I (21) |
| 246 | #define INT1_LO_CAN1_BUF14I (22) |
| 247 | #define INT1_LO_CAN1_BUF15I (23) |
| 248 | #define INT1_LO_CAN1_ERRINT (24) |
| 249 | #define INT1_LO_CAN1_BOFFINT (25) |
| 250 | /* 26 Reserved */ |
| 251 | #define INT1_LO_ETPU_TC0F (27) |
| 252 | #define INT1_LO_ETPU_TC1F (28) |
| 253 | #define INT1_LO_ETPU_TC2F (29) |
| 254 | #define INT1_LO_ETPU_TC3F (30) |
| 255 | #define INT1_LO_ETPU_TC4F (31) |
| 256 | #define INT1_HI_ETPU_TC5F (32) |
| 257 | #define INT1_HI_ETPU_TC6F (33) |
| 258 | #define INT1_HI_ETPU_TC7F (34) |
| 259 | #define INT1_HI_ETPU_TC8F (35) |
| 260 | #define INT1_HI_ETPU_TC9F (36) |
| 261 | #define INT1_HI_ETPU_TC10F (37) |
| 262 | #define INT1_HI_ETPU_TC11F (38) |
| 263 | #define INT1_HI_ETPU_TC12F (39) |
| 264 | #define INT1_HI_ETPU_TC13F (40) |
| 265 | #define INT1_HI_ETPU_TC14F (41) |
| 266 | #define INT1_HI_ETPU_TC15F (42) |
| 267 | #define INT1_HI_ETPU_TC16F (43) |
| 268 | #define INT1_HI_ETPU_TC17F (44) |
| 269 | #define INT1_HI_ETPU_TC18F (45) |
| 270 | #define INT1_HI_ETPU_TC19F (46) |
| 271 | #define INT1_HI_ETPU_TC20F (47) |
| 272 | #define INT1_HI_ETPU_TC21F (48) |
| 273 | #define INT1_HI_ETPU_TC22F (49) |
| 274 | #define INT1_HI_ETPU_TC23F (50) |
| 275 | #define INT1_HI_ETPU_TC24F (51) |
| 276 | #define INT1_HI_ETPU_TC25F (52) |
| 277 | #define INT1_HI_ETPU_TC26F (53) |
| 278 | #define INT1_HI_ETPU_TC27F (54) |
| 279 | #define INT1_HI_ETPU_TC28F (55) |
| 280 | #define INT1_HI_ETPU_TC29F (56) |
| 281 | #define INT1_HI_ETPU_TC30F (57) |
| 282 | #define INT1_HI_ETPU_TC31F (58) |
| 283 | #define INT1_HI_ETPU_TGIF (59) |
| 284 | |
| TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 285 | /********************************************************************* |
| 286 | * General Purpose I/O (GPIO) |
| 287 | *********************************************************************/ |
| 288 | /* Bit definitions and macros for GPIO_PODR */ |
| 289 | #define GPIO_PODR_ADDR(x) (((x)&0x07)<<5) |
| 290 | #define GPIO_PODR_ADDR_MASK (0xE0) |
| 291 | #define GPIO_PODR_BS(x) ((x)&0x0F) |
| 292 | #define GPIO_PODR_BS_MASK (0x0F) |
| 293 | #define GPIO_PODR_CS(x) (((x)&0x7F)<<1) |
| 294 | #define GPIO_PODR_CS_MASK (0xFE) |
| 295 | #define GPIO_PODR_SDRAM(X) ((x)&0x3F) |
| 296 | #define GPIO_PODR_SDRAM_MASK (0x3F) |
| 297 | #define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x) |
| 298 | #define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK |
| 299 | #define GPIO_PODR_UARTH(x) ((x)&0x03) |
| 300 | #define GPIO_PODR_UARTH_MASK (0x03) |
| 301 | #define GPIO_PODR_QSPI(x) ((x)&0x1F) |
| 302 | #define GPIO_PODR_QSPI_MASK (0x1F) |
| 303 | #define GPIO_PODR_ETPU(x) ((x)&0x07) |
| 304 | #define GPIO_PODR_ETPU_MASK (0x07) |
| 305 | |
| 306 | /* Bit definitions and macros for GPIO_PDDR */ |
| 307 | #define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x) |
| 308 | #define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK |
| 309 | #define GPIO_PDDR_BS(x) GPIO_PODR_BS(x) |
| 310 | #define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK |
| 311 | #define GPIO_PDDR_CS(x) GPIO_PODR_CS(x) |
| 312 | #define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK |
| 313 | #define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X) |
| 314 | #define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK |
| 315 | #define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x) |
| 316 | #define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK |
| 317 | #define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x) |
| 318 | #define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK |
| 319 | #define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x) |
| 320 | #define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK |
| 321 | #define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x) |
| 322 | #define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK |
| 323 | |
| 324 | /* Bit definitions and macros for GPIO_PPDSDR */ |
| 325 | #define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x) |
| 326 | #define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK |
| 327 | #define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x) |
| 328 | #define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK |
| 329 | #define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x) |
| 330 | #define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK |
| 331 | #define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X) |
| 332 | #define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK |
| 333 | #define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x) |
| 334 | #define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK |
| 335 | #define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x) |
| 336 | #define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK |
| 337 | #define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x) |
| 338 | #define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK |
| 339 | #define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x) |
| 340 | #define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK |
| 341 | |
| 342 | /* Bit definitions and macros for GPIO_PCLRR */ |
| 343 | #define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x) |
| 344 | #define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK |
| 345 | #define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x) |
| 346 | #define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK |
| 347 | #define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x) |
| 348 | #define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK |
| 349 | #define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X) |
| 350 | #define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK |
| 351 | #define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x) |
| 352 | #define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK |
| 353 | #define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x) |
| 354 | #define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK |
| 355 | #define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x) |
| 356 | #define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK |
| 357 | #define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x) |
| 358 | #define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK |
| 359 | |
| 360 | /* Bit definitions and macros for GPIO_PAR */ |
| 361 | #define GPIO_PAR_AD_ADDR23 (0x80) |
| 362 | #define GPIO_PAR_AD_ADDR22 (0x40) |
| 363 | #define GPIO_PAR_AD_ADDR21 (0x20) |
| 364 | #define GPIO_PAR_AD_DATAL (0x01) |
| 365 | #define GPIO_PAR_BUSCTL_OE (0x4000) |
| 366 | #define GPIO_PAR_BUSCTL_TA (0x1000) |
| 367 | #define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10) |
| 368 | #define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00) |
| 369 | #define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400) |
| 370 | #define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800) |
| 371 | #define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00) |
| 372 | #define GPIO_PAR_BUSCTL_RWB (0x0100) |
| 373 | #define GPIO_PAR_BUSCTL_TSIZ1 (0x0040) |
| 374 | #define GPIO_PAR_BUSCTL_TSIZ0 (0x0010) |
| 375 | #define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2) |
| 376 | #define GPIO_PAR_BUSCTL_TS_MASK (0x0C) |
| 377 | #define GPIO_PAR_BUSCTL_TS_GPIO (0x04) |
| 378 | #define GPIO_PAR_BUSCTL_TS_DACK2 (0x08) |
| 379 | #define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C) |
| 380 | #define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03) |
| 381 | #define GPIO_PAR_BUSCTL_TIP_MASK (0x03) |
| 382 | #define GPIO_PAR_BUSCTL_TIP_GPIO (0x01) |
| 383 | #define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02) |
| 384 | #define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03) |
| 385 | #define GPIO_PAR_BS(x) ((x)&0x0F) |
| 386 | #define GPIO_PAR_BS_MASK (0x0F) |
| 387 | #define GPIO_PAR_CS(x) (((x)&0x7F)<<1) |
| 388 | #define GPIO_PAR_CS_MASK (0xFE) |
| 389 | #define GPIO_PAR_CS_CS7 (0x80) |
| 390 | #define GPIO_PAR_CS_CS6 (0x40) |
| 391 | #define GPIO_PAR_CS_CS5 (0x20) |
| 392 | #define GPIO_PAR_CS_CS4 (0x10) |
| 393 | #define GPIO_PAR_CS_CS3 (0x08) |
| 394 | #define GPIO_PAR_CS_CS2 (0x04) |
| 395 | #define GPIO_PAR_CS_CS1 (0x02) |
| 396 | #define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3 |
| 397 | #define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2 |
| 398 | #define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6) |
| 399 | #define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0) |
| 400 | #define GPIO_PAR_SDRAM_SDWE (0x20) |
| 401 | #define GPIO_PAR_SDRAM_SCAS (0x10) |
| 402 | #define GPIO_PAR_SDRAM_SRAS (0x08) |
| 403 | #define GPIO_PAR_SDRAM_SCKE (0x04) |
| 404 | #define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03) |
| 405 | #define GPIO_PAR_SDRAM_SDCS_MASK (0x03) |
| 406 | #define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6) |
| 407 | #define GPIO_PAR_FECI2C_EMDC_MASK (0xC0) |
| 408 | #define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40) |
| 409 | #define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80) |
| 410 | #define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0) |
| 411 | #define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4) |
| 412 | #define GPIO_PAR_FECI2C_EMDIO_MASK (0x30) |
| 413 | #define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10) |
| 414 | #define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20) |
| 415 | #define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30) |
| 416 | #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2) |
| 417 | #define GPIO_PAR_FECI2C_SCL_MASK (0x0C) |
| 418 | #define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08) |
| 419 | #define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C) |
| 420 | #define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03) |
| 421 | #define GPIO_PAR_FECI2C_SDA_MASK (0x03) |
| 422 | #define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02) |
| 423 | #define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03) |
| 424 | #define GPIO_PAR_UART_DREQ2 (0x8000) |
| 425 | #define GPIO_PAR_UART_CAN1EN (0x4000) |
| 426 | #define GPIO_PAR_UART_U2RXD (0x2000) |
| 427 | #define GPIO_PAR_UART_U2TXD (0x1000) |
| 428 | #define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10) |
| 429 | #define GPIO_PAR_UART_U1RXD_MASK (0x0C00) |
| 430 | #define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800) |
| 431 | #define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) |
| 432 | #define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8) |
| 433 | #define GPIO_PAR_UART_U1TXD_MASK (0x0300) |
| 434 | #define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200) |
| 435 | #define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) |
| 436 | #define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6) |
| 437 | #define GPIO_PAR_UART_U1CTS_MASK (0x00C0) |
| 438 | #define GPIO_PAR_UART_U1CTS_U2CTS (0x0080) |
| 439 | #define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0) |
| 440 | #define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4) |
| 441 | #define GPIO_PAR_UART_U1RTS_MASK (0x0030) |
| 442 | #define GPIO_PAR_UART_U1RTS_U2RTS (0x0020) |
| 443 | #define GPIO_PAR_UART_U1RTS_U1RTS (0x0030) |
| 444 | #define GPIO_PAR_UART_U0RXD (0x0008) |
| 445 | #define GPIO_PAR_UART_U0TXD (0x0004) |
| 446 | #define GPIO_PAR_UART_U0CTS (0x0002) |
| 447 | #define GPIO_PAR_UART_U0RTS (0x0001) |
| 448 | #define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6) |
| 449 | #define GPIO_PAR_QSPI_CS1_MASK (0xC0) |
| 450 | #define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80) |
| 451 | #define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0) |
| 452 | #define GPIO_PAR_QSPI_CS0 (0x20) |
| 453 | #define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3) |
| 454 | #define GPIO_PAR_QSPI_DIN_MASK (0x18) |
| 455 | #define GPIO_PAR_QSPI_DIN_I2CSDA (0x10) |
| 456 | #define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18) |
| 457 | #define GPIO_PAR_QSPI_DOUT (0x04) |
| 458 | #define GPIO_PAR_QSPI_SCK(x) ((x)&0x03) |
| 459 | #define GPIO_PAR_QSPI_SCK_MASK (0x03) |
| 460 | #define GPIO_PAR_QSPI_SCK_I2CSCL (0x02) |
| 461 | #define GPIO_PAR_QSPI_SCK_QSPISCK (0x03) |
| 462 | #define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14) |
| 463 | #define GPIO_PAR_DT3IN_MASK (0xC000) |
| 464 | #define GPIO_PAR_DT3IN_QSPICS2 (0x4000) |
| 465 | #define GPIO_PAR_DT3IN_U2CTS (0x8000) |
| 466 | #define GPIO_PAR_DT3IN_DT3IN (0xC000) |
| 467 | #define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12) |
| 468 | #define GPIO_PAR_DT2IN_MASK (0x3000) |
| 469 | #define GPIO_PAR_DT2IN_DT2OUT (0x1000) |
| 470 | #define GPIO_PAR_DT2IN_DREQ2 (0x2000) |
| 471 | #define GPIO_PAR_DT2IN_DT2IN (0x3000) |
| 472 | #define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10) |
| 473 | #define GPIO_PAR_DT1IN_MASK (0x0C00) |
| 474 | #define GPIO_PAR_DT1IN_DT1OUT (0x0400) |
| 475 | #define GPIO_PAR_DT1IN_DREQ1 (0x0800) |
| 476 | #define GPIO_PAR_DT1IN_DT1IN (0x0C00) |
| 477 | #define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8) |
| 478 | #define GPIO_PAR_DT0IN_MASK (0x0300) |
| 479 | #define GPIO_PAR_DT0IN_DREQ0 (0x0200) |
| 480 | #define GPIO_PAR_DT0IN_DT0IN (0x0300) |
| 481 | #define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6) |
| 482 | #define GPIO_PAR_DT3OUT_MASK (0x00C0) |
| 483 | #define GPIO_PAR_DT3OUT_QSPICS3 (0x0040) |
| 484 | #define GPIO_PAR_DT3OUT_U2RTS (0x0080) |
| 485 | #define GPIO_PAR_DT3OUT_DT3OUT (0x00C0) |
| 486 | #define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4) |
| 487 | #define GPIO_PAR_DT2OUT_MASK (0x0030) |
| 488 | #define GPIO_PAR_DT2OUT_DACK2 (0x0020) |
| 489 | #define GPIO_PAR_DT2OUT_DT2OUT (0x0030) |
| 490 | #define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2) |
| 491 | #define GPIO_PAR_DT1OUT_MASK (0x000C) |
| 492 | #define GPIO_PAR_DT1OUT_DACK1 (0x0008) |
| 493 | #define GPIO_PAR_DT1OUT_DT1OUT (0x000C) |
| 494 | #define GPIO_PAR_DT0OUT(x) ((x)&0x03) |
| 495 | #define GPIO_PAR_DT0OUT_MASK (0x0003) |
| 496 | #define GPIO_PAR_DT0OUT_DACK0 (0x0002) |
| 497 | #define GPIO_PAR_DT0OUT_DT0OUT (0x0003) |
| 498 | #define GPIO_PAR_ETPU_TCRCLK (0x04) |
| 499 | #define GPIO_PAR_ETPU_UTPU_ODIS (0x02) |
| 500 | #define GPIO_PAR_ETPU_LTPU_ODIS (0x01) |
| 501 | |
| 502 | /* Bit definitions and macros for GPIO_DSCR */ |
| 503 | #define GPIO_DSCR_EIM_EIM1 (0x10) |
| 504 | #define GPIO_DSCR_EIM_EIM0 (0x01) |
| 505 | #define GPIO_DSCR_ETPU_ETPU31_24 (0x40) |
| 506 | #define GPIO_DSCR_ETPU_ETPU23_16 (0x10) |
| 507 | #define GPIO_DSCR_ETPU_ETPU15_8 (0x04) |
| 508 | #define GPIO_DSCR_ETPU_ETPU7_0 (0x01) |
| 509 | #define GPIO_DSCR_FECI2C_FEC (0x10) |
| 510 | #define GPIO_DSCR_FECI2C_I2C (0x01) |
| 511 | #define GPIO_DSCR_UART_IRQ (0x40) |
| 512 | #define GPIO_DSCR_UART_UART2 (0x10) |
| 513 | #define GPIO_DSCR_UART_UART1 (0x04) |
| 514 | #define GPIO_DSCR_UART_UART0 (0x01) |
| 515 | #define GPIO_DSCR_QSPI_QSPI (0x01) |
| 516 | #define GPIO_DSCR_TIMER (0x01) |
| 517 | |
| 518 | /********************************************************************* |
| 519 | * Chip Configuration Module (CCM) |
| 520 | *********************************************************************/ |
| 521 | /* Bit definitions and macros for CCM_RCR */ |
| 522 | #define CCM_RCR_SOFTRST (0x80) |
| 523 | #define CCM_RCR_FRCRSTOUT (0x40) |
| 524 | |
| 525 | /* Bit definitions and macros for CCM_RSR */ |
| 526 | #define CCM_RSR_SOFT (0x20) |
| 527 | #define CCM_RSR_WDR (0x10) |
| 528 | #define CCM_RSR_POR (0x08) |
| 529 | #define CCM_RSR_EXT (0x04) |
| 530 | #define CCM_RSR_LOC (0x02) |
| 531 | #define CCM_RSR_LOL (0x01) |
| 532 | |
| 533 | /* Bit definitions and macros for CCM_CCR */ |
| 534 | #define CCM_CCR_LOAD (0x8000) |
| 535 | #define CCM_CCR_SZEN (0x0040) |
| 536 | #define CCM_CCR_PSTEN (0x0020) |
| 537 | #define CCM_CCR_BME (0x0008) |
| 538 | #define CCM_CCR_BMT(x) ((x)&0x07) |
| 539 | #define CCM_CCR_BMT_MASK (0x0007) |
| 540 | #define CCM_CCR_BMT_64K (0x0000) |
| 541 | #define CCM_CCR_BMT_32K (0x0001) |
| 542 | #define CCM_CCR_BMT_16K (0x0002) |
| 543 | #define CCM_CCR_BMT_8K (0x0003) |
| 544 | #define CCM_CCR_BMT_4K (0x0004) |
| 545 | #define CCM_CCR_BMT_2K (0x0005) |
| 546 | #define CCM_CCR_BMT_1K (0x0006) |
| 547 | #define CCM_CCR_BMT_512 (0x0007) |
| 548 | |
| 549 | /* Bit definitions and macros for CCM_RCON */ |
| 550 | #define CCM_RCON_RCSC(x) (((x)&0x0003)<<8) |
| 551 | #define CCM_RCON_RLOAD (0x0020) |
| 552 | #define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) |
| 553 | #define CCM_RCON_BOOTPS_MASK (0x0018) |
| 554 | #define CCM_RCON_BOOTPS_32 (0x0018) |
| 555 | #define CCM_RCON_BOOTPS_16 (0x0008) |
| 556 | #define CCM_RCON_BOOTPS_8 (0x0010) |
| 557 | #define CCM_RCON_MODE (0x0001) |
| 558 | |
| 559 | /* Bit definitions and macros for CCM_CIR */ |
| 560 | #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) |
| 561 | #define CCM_CIR_PRN(x) ((x)&0x003F) |
| 562 | |
| 563 | /********************************************************************* |
| 564 | * PLL Clock Module |
| 565 | *********************************************************************/ |
| 566 | /* Bit definitions and macros for PLL_SYNCR */ |
| 567 | #define PLL_SYNCR_MFD(x) (((x)&0x07)<<24) |
| 568 | #define PLL_SYNCR_MFD_MASK (0x07000000) |
| 569 | #define PLL_SYNCR_RFC(x) (((x)&0x07)<<19) |
| 570 | #define PLL_SYNCR_RFC_MASK (0x00380000) |
| 571 | #define PLL_SYNCR_LOCEN (0x00040000) |
| 572 | #define PLL_SYNCR_LOLRE (0x00020000) |
| 573 | #define PLL_SYNCR_LOCRE (0x00010000) |
| 574 | #define PLL_SYNCR_DISCLK (0x00008000) |
| 575 | #define PLL_SYNCR_LOLIRQ (0x00004000) |
| 576 | #define PLL_SYNCR_LOCIRQ (0x00002000) |
| 577 | #define PLL_SYNCR_RATE (0x00001000) |
| 578 | #define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10) |
| 579 | #define PLL_SYNCR_EXP(x) ((x)&0x03FF) |
| 580 | |
| 581 | /* Bit definitions and macros for PLL_SYNSR */ |
| 582 | #define PLL_SYNSR_LOLF (0x00000200) |
| 583 | #define PLL_SYNSR_LOC (0x00000100) |
| 584 | #define PLL_SYNSR_MODE (0x00000080) |
| 585 | #define PLL_SYNSR_PLLSEL (0x00000040) |
| 586 | #define PLL_SYNSR_PLLREF (0x00000020) |
| 587 | #define PLL_SYNSR_LOCKS (0x00000010) |
| 588 | #define PLL_SYNSR_LOCK (0x00000008) |
| 589 | #define PLL_SYNSR_LOCF (0x00000004) |
| 590 | #define PLL_SYNSR_CALDONE (0x00000002) |
| 591 | #define PLL_SYNSR_CALPASS (0x00000001) |
| 592 | |
| 593 | /********************************************************************* |
| TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 594 | * Watchdog Timer Modules (WTM) |
| 595 | *********************************************************************/ |
| 596 | /* Bit definitions and macros for WTM_WCR */ |
| 597 | #define WTM_WCR_WAIT (0x0008) |
| 598 | #define WTM_WCR_DOZE (0x0004) |
| 599 | #define WTM_WCR_HALTED (0x0002) |
| 600 | #define WTM_WCR_EN (0x0001) |
| 601 | |
| TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 602 | #endif /* mcf5235_h */ |