| Carlo Caione | 4b3ab59 | 2016-06-10 20:18:22 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Configuration for Amlogic Meson GXBB SoCs |
| 3 | * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef __MESON_GXBB_COMMON_CONFIG_H |
| 9 | #define __MESON_GXBB_COMMON_CONFIG_H |
| 10 | |
| 11 | #define CONFIG_CPU_ARMV8 |
| 12 | #define CONFIG_REMAKE_ELF |
| 13 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
| 14 | #define CONFIG_SYS_NO_FLASH |
| 15 | #define CONFIG_NR_DRAM_BANKS 1 |
| 16 | #define CONFIG_ENV_IS_NOWHERE 1 |
| 17 | #define CONFIG_ENV_SIZE 0x2000 |
| 18 | #define CONFIG_SYS_MAXARGS 32 |
| 19 | #define CONFIG_SYS_MALLOC_LEN (32 << 20) |
| 20 | #define CONFIG_SYS_CBSIZE 1024 |
| 21 | #define CONFIG_MISC_INIT_R |
| 22 | |
| 23 | #define CONFIG_SYS_SDRAM_BASE 0 |
| 24 | #define CONFIG_SYS_TEXT_BASE 0x01000000 |
| 25 | #define CONFIG_SYS_INIT_SP_ADDR 0x20000000 |
| 26 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE |
| 27 | |
| 28 | /* Generic Interrupt Controller Definitions */ |
| 29 | #define GICD_BASE 0xc4301000 |
| 30 | #define GICC_BASE 0xc4302000 |
| 31 | |
| 32 | #define CONFIG_CMD_ENV |
| 33 | |
| 34 | /* Monitor Command Prompt */ |
| 35 | /* Console I/O Buffer Size */ |
| 36 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 37 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 38 | #define CONFIG_SYS_HUSH_PARSER |
| 39 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 40 | #define CONFIG_SYS_LONGHELP |
| 41 | #define CONFIG_CMDLINE_EDITING |
| 42 | |
| 43 | #include <config_distro_defaults.h> |
| 44 | |
| 45 | #endif /* __MESON_GXBB_COMMON_CONFIG_H */ |