| Bin Meng | 77eae0e | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | |
| 3 | / { |
| 4 | cpus { |
| 5 | u-boot,dm-spl; |
| 6 | CPU0: cpu@0 { |
| 7 | u-boot,dm-spl; |
| 8 | CPU0_intc: interrupt-controller { |
| 9 | u-boot,dm-spl; |
| 10 | }; |
| 11 | }; |
| 12 | CPU1: cpu@1 { |
| 13 | u-boot,dm-spl; |
| 14 | CPU1_intc: interrupt-controller { |
| 15 | u-boot,dm-spl; |
| 16 | }; |
| 17 | }; |
| 18 | CPU2: cpu@2 { |
| 19 | u-boot,dm-spl; |
| 20 | CPU2_intc: interrupt-controller { |
| 21 | u-boot,dm-spl; |
| 22 | }; |
| 23 | }; |
| 24 | CPU3: cpu@3 { |
| 25 | u-boot,dm-spl; |
| 26 | CPU3_intc: interrupt-controller { |
| 27 | u-boot,dm-spl; |
| 28 | }; |
| 29 | }; |
| 30 | }; |
| 31 | |
| 32 | memory@0 { |
| 33 | u-boot,dm-spl; |
| 34 | }; |
| 35 | |
| 36 | soc { |
| 37 | u-boot,dm-spl; |
| 38 | |
| Yu Chien Peter Lin | a5dfa3b | 2022-10-25 23:03:50 +0800 | [diff] [blame] | 39 | plicsw: interrupt-controller@e6400000 { |
| Bin Meng | 77eae0e | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 40 | u-boot,dm-spl; |
| 41 | }; |
| 42 | |
| 43 | plmt0@e6000000 { |
| 44 | u-boot,dm-spl; |
| 45 | }; |
| 46 | }; |
| 47 | |
| 48 | serial0: serial@f0300000 { |
| 49 | u-boot,dm-spl; |
| 50 | }; |
| 51 | |
| 52 | }; |