blob: 67dc3c4588ee015533bb6ddc3720f97d208958dd [file] [log] [blame]
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +09001/*
2 * R8A66597 HCD (Host Controller Driver) for u-boot
3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 *
Simon Glasse62b5262015-07-06 16:47:42 -06006 * SPDX-License-Identifier: GPL-2.0
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +09007 */
8
9#ifndef __R8A66597_H__
10#define __R8A66597_H__
11
12#define SYSCFG0 0x00
13#define SYSCFG1 0x02
14#define SYSSTS0 0x04
15#define SYSSTS1 0x06
16#define DVSTCTR0 0x08
17#define DVSTCTR1 0x0A
18#define TESTMODE 0x0C
19#define PINCFG 0x0E
20#define DMA0CFG 0x10
21#define DMA1CFG 0x12
22#define CFIFO 0x14
23#define D0FIFO 0x18
24#define D1FIFO 0x1C
25#define CFIFOSEL 0x20
26#define CFIFOCTR 0x22
27#define CFIFOSIE 0x24
28#define D0FIFOSEL 0x28
29#define D0FIFOCTR 0x2A
30#define D1FIFOSEL 0x2C
31#define D1FIFOCTR 0x2E
32#define INTENB0 0x30
33#define INTENB1 0x32
34#define INTENB2 0x34
35#define BRDYENB 0x36
36#define NRDYENB 0x38
37#define BEMPENB 0x3A
38#define SOFCFG 0x3C
39#define INTSTS0 0x40
40#define INTSTS1 0x42
41#define INTSTS2 0x44
42#define BRDYSTS 0x46
43#define NRDYSTS 0x48
44#define BEMPSTS 0x4A
45#define FRMNUM 0x4C
46#define UFRMNUM 0x4E
47#define USBADDR 0x50
48#define USBREQ 0x54
49#define USBVAL 0x56
50#define USBINDX 0x58
51#define USBLENG 0x5A
52#define DCPCFG 0x5C
53#define DCPMAXP 0x5E
54#define DCPCTR 0x60
55#define PIPESEL 0x64
56#define PIPECFG 0x68
57#define PIPEBUF 0x6A
58#define PIPEMAXP 0x6C
59#define PIPEPERI 0x6E
60#define PIPE1CTR 0x70
61#define PIPE2CTR 0x72
62#define PIPE3CTR 0x74
63#define PIPE4CTR 0x76
64#define PIPE5CTR 0x78
65#define PIPE6CTR 0x7A
66#define PIPE7CTR 0x7C
67#define PIPE8CTR 0x7E
68#define PIPE9CTR 0x80
69#define PIPE1TRE 0x90
70#define PIPE1TRN 0x92
71#define PIPE2TRE 0x94
72#define PIPE2TRN 0x96
73#define PIPE3TRE 0x98
74#define PIPE3TRN 0x9A
75#define PIPE4TRE 0x9C
76#define PIPE4TRN 0x9E
77#define PIPE5TRE 0xA0
78#define PIPE5TRN 0xA2
79#define DEVADD0 0xD0
80#define DEVADD1 0xD2
81#define DEVADD2 0xD4
82#define DEVADD3 0xD6
83#define DEVADD4 0xD8
84#define DEVADD5 0xDA
85#define DEVADD6 0xDC
86#define DEVADD7 0xDE
87#define DEVADD8 0xE0
88#define DEVADD9 0xE2
89#define DEVADDA 0xE4
90
91/* System Configuration Control Register */
92#define XTAL 0xC000 /* b15-14: Crystal selection */
93#define XTAL48 0x8000 /* 48MHz */
94#define XTAL24 0x4000 /* 24MHz */
95#define XTAL12 0x0000 /* 12MHz */
96#define XCKE 0x2000 /* b13: External clock enable */
97#define PLLC 0x0800 /* b11: PLL control */
98#define SCKE 0x0400 /* b10: USB clock enable */
99#define PCSDIS 0x0200 /* b9: not CS wakeup */
100#define LPSME 0x0100 /* b8: Low power sleep mode */
101#define HSE 0x0080 /* b7: Hi-speed enable */
102#define DCFM 0x0040 /* b6: Controller function select */
103#define DRPD 0x0020 /* b5: D+/- pull down control */
104#define DPRPU 0x0010 /* b4: D+ pull up control */
105#define USBE 0x0001 /* b0: USB module operation enable */
106
107/* System Configuration Status Register */
108#define OVCBIT 0x8000 /* b15-14: Over-current bit */
109#define OVCMON 0xC000 /* b15-14: Over-current monitor */
110#define SOFEA 0x0020 /* b5: SOF monitor */
111#define IDMON 0x0004 /* b3: ID-pin monitor */
112#define LNST 0x0003 /* b1-0: D+, D- line status */
113#define SE1 0x0003 /* SE1 */
114#define FS_KSTS 0x0002 /* Full-Speed K State */
115#define FS_JSTS 0x0001 /* Full-Speed J State */
116#define LS_JSTS 0x0002 /* Low-Speed J State */
117#define LS_KSTS 0x0001 /* Low-Speed K State */
118#define SE0 0x0000 /* SE0 */
119
120/* Device State Control Register */
121#define EXTLP0 0x0400 /* b10: External port */
122#define VBOUT 0x0200 /* b9: VBUS output */
123#define WKUP 0x0100 /* b8: Remote wakeup */
124#define RWUPE 0x0080 /* b7: Remote wakeup sense */
125#define USBRST 0x0040 /* b6: USB reset enable */
126#define RESUME 0x0020 /* b5: Resume enable */
127#define UACT 0x0010 /* b4: USB bus enable */
128#define RHST 0x0007 /* b1-0: Reset handshake status */
129#define HSPROC 0x0004 /* HS handshake is processing */
130#define HSMODE 0x0003 /* Hi-Speed mode */
131#define FSMODE 0x0002 /* Full-Speed mode */
132#define LSMODE 0x0001 /* Low-Speed mode */
133#define UNDECID 0x0000 /* Undecided */
134
135/* Test Mode Register */
136#define UTST 0x000F /* b3-0: Test select */
137#define H_TST_PACKET 0x000C /* HOST TEST Packet */
138#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
139#define H_TST_K 0x000A /* HOST TEST K */
140#define H_TST_J 0x0009 /* HOST TEST J */
141#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
142#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
143#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
144#define P_TST_K 0x0002 /* PERI TEST K */
145#define P_TST_J 0x0001 /* PERI TEST J */
146#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
147
148/* Data Pin Configuration Register */
149#define LDRV 0x8000 /* b15: Drive Current Adjust */
150#define VIF1 0x0000 /* VIF = 1.8V */
151#define VIF3 0x8000 /* VIF = 3.3V */
152#define INTA 0x0001 /* b1: USB INT-pin active */
153
154/* DMAx Pin Configuration Register */
155#define DREQA 0x4000 /* b14: Dreq active select */
156#define BURST 0x2000 /* b13: Burst mode */
157#define DACKA 0x0400 /* b10: Dack active select */
158#define DFORM 0x0380 /* b9-7: DMA mode select */
159#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
160#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
161#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
162#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
163#define DENDA 0x0040 /* b6: Dend active select */
164#define PKTM 0x0020 /* b5: Packet mode */
165#define DENDE 0x0010 /* b4: Dend enable */
166#define OBUS 0x0004 /* b2: OUTbus mode */
167
168/* CFIFO/DxFIFO Port Select Register */
169#define RCNT 0x8000 /* b15: Read count mode */
170#define REW 0x4000 /* b14: Buffer rewind */
171#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
172#define DREQE 0x1000 /* b12: DREQ output enable */
173#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
174#define MBW 0x0800
175#else
176#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
177#endif
178#define MBW_8 0x0000 /* 8bit */
179#define MBW_16 0x0400 /* 16bit */
180#define BIGEND 0x0100 /* b8: Big endian mode */
181#define BYTE_LITTLE 0x0000 /* little dendian */
182#define BYTE_BIG 0x0100 /* big endifan */
183#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
184#define CURPIPE 0x000F /* b2-0: PIPE select */
185
186/* CFIFO/DxFIFO Port Control Register */
187#define BVAL 0x8000 /* b15: Buffer valid flag */
188#define BCLR 0x4000 /* b14: Buffer clear */
189#define FRDY 0x2000 /* b13: FIFO ready */
190#define DTLN 0x0FFF /* b11-0: FIFO received data length */
191
192/* Interrupt Enable Register 0 */
193#define VBSE 0x8000 /* b15: VBUS interrupt */
194#define RSME 0x4000 /* b14: Resume interrupt */
195#define SOFE 0x2000 /* b13: Frame update interrupt */
196#define DVSE 0x1000 /* b12: Device state transition interrupt */
197#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
198#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
199#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
200#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
201
202/* Interrupt Enable Register 1 */
203#define OVRCRE 0x8000 /* b15: Over-current interrupt */
204#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
205#define DTCHE 0x1000 /* b12: Detach sense interrupt */
206#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
207#define EOFERRE 0x0040 /* b6: EOF error interrupt */
208#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
209#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
210
211/* BRDY Interrupt Enable/Status Register */
212#define BRDY9 0x0200 /* b9: PIPE9 */
213#define BRDY8 0x0100 /* b8: PIPE8 */
214#define BRDY7 0x0080 /* b7: PIPE7 */
215#define BRDY6 0x0040 /* b6: PIPE6 */
216#define BRDY5 0x0020 /* b5: PIPE5 */
217#define BRDY4 0x0010 /* b4: PIPE4 */
218#define BRDY3 0x0008 /* b3: PIPE3 */
219#define BRDY2 0x0004 /* b2: PIPE2 */
220#define BRDY1 0x0002 /* b1: PIPE1 */
221#define BRDY0 0x0001 /* b1: PIPE0 */
222
223/* NRDY Interrupt Enable/Status Register */
224#define NRDY9 0x0200 /* b9: PIPE9 */
225#define NRDY8 0x0100 /* b8: PIPE8 */
226#define NRDY7 0x0080 /* b7: PIPE7 */
227#define NRDY6 0x0040 /* b6: PIPE6 */
228#define NRDY5 0x0020 /* b5: PIPE5 */
229#define NRDY4 0x0010 /* b4: PIPE4 */
230#define NRDY3 0x0008 /* b3: PIPE3 */
231#define NRDY2 0x0004 /* b2: PIPE2 */
232#define NRDY1 0x0002 /* b1: PIPE1 */
233#define NRDY0 0x0001 /* b1: PIPE0 */
234
235/* BEMP Interrupt Enable/Status Register */
236#define BEMP9 0x0200 /* b9: PIPE9 */
237#define BEMP8 0x0100 /* b8: PIPE8 */
238#define BEMP7 0x0080 /* b7: PIPE7 */
239#define BEMP6 0x0040 /* b6: PIPE6 */
240#define BEMP5 0x0020 /* b5: PIPE5 */
241#define BEMP4 0x0010 /* b4: PIPE4 */
242#define BEMP3 0x0008 /* b3: PIPE3 */
243#define BEMP2 0x0004 /* b2: PIPE2 */
244#define BEMP1 0x0002 /* b1: PIPE1 */
245#define BEMP0 0x0001 /* b0: PIPE0 */
246
247/* SOF Pin Configuration Register */
248#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
249#define BRDYM 0x0040 /* b6: BRDY clear timing */
250#define INTL 0x0020 /* b5: Interrupt sense select */
251#define EDGESTS 0x0010 /* b4: */
252#define SOFMODE 0x000C /* b3-2: SOF pin select */
253#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
254#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
255#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
256
257/* Interrupt Status Register 0 */
258#define VBINT 0x8000 /* b15: VBUS interrupt */
259#define RESM 0x4000 /* b14: Resume interrupt */
260#define SOFR 0x2000 /* b13: SOF frame update interrupt */
261#define DVST 0x1000 /* b12: Device state transition interrupt */
262#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
263#define BEMP 0x0400 /* b10: Buffer empty interrupt */
264#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
265#define BRDY 0x0100 /* b8: Buffer ready interrupt */
266#define VBSTS 0x0080 /* b7: VBUS input port */
267#define DVSQ 0x0070 /* b6-4: Device state */
268#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
269#define DS_SPD_ADDR 0x0060 /* Suspend Address */
270#define DS_SPD_DFLT 0x0050 /* Suspend Default */
271#define DS_SPD_POWR 0x0040 /* Suspend Powered */
272#define DS_SUSP 0x0040 /* Suspend */
273#define DS_CNFG 0x0030 /* Configured */
274#define DS_ADDS 0x0020 /* Address */
275#define DS_DFLT 0x0010 /* Default */
276#define DS_POWR 0x0000 /* Powered */
277#define DVSQS 0x0030 /* b5-4: Device state */
278#define VALID 0x0008 /* b3: Setup packet detected flag */
279#define CTSQ 0x0007 /* b2-0: Control transfer stage */
280#define CS_SQER 0x0006 /* Sequence error */
281#define CS_WRND 0x0005 /* Control write nodata status stage */
282#define CS_WRSS 0x0004 /* Control write status stage */
283#define CS_WRDS 0x0003 /* Control write data stage */
284#define CS_RDSS 0x0002 /* Control read status stage */
285#define CS_RDDS 0x0001 /* Control read data stage */
286#define CS_IDST 0x0000 /* Idle or setup stage */
287
288/* Interrupt Status Register 1 */
289#define OVRCR 0x8000 /* b15: Over-current interrupt */
290#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
291#define DTCH 0x1000 /* b12: Detach sense interrupt */
292#define ATTCH 0x0800 /* b11: Attach sense interrupt */
293#define EOFERR 0x0040 /* b6: EOF-error interrupt */
294#define SIGN 0x0020 /* b5: Setup ignore interrupt */
295#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
296
297/* Frame Number Register */
298#define OVRN 0x8000 /* b15: Overrun error */
299#define CRCE 0x4000 /* b14: Received data error */
300#define FRNM 0x07FF /* b10-0: Frame number */
301
302/* Micro Frame Number Register */
303#define UFRNM 0x0007 /* b2-0: Micro frame number */
304
305/* Default Control Pipe Maxpacket Size Register */
306/* Pipe Maxpacket Size Register */
307#define DEVSEL 0xF000 /* b15-14: Device address select */
308#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
309
310/* Default Control Pipe Control Register */
311#define BSTS 0x8000 /* b15: Buffer status */
312#define SUREQ 0x4000 /* b14: Send USB request */
313#define CSCLR 0x2000 /* b13: complete-split status clear */
314#define CSSTS 0x1000 /* b12: complete-split status */
315#define SUREQCLR 0x0800 /* b11: stop setup request */
316#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
317#define SQSET 0x0080 /* b7: Sequence toggle bit set */
318#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
319#define PBUSY 0x0020 /* b5: pipe busy */
320#define PINGE 0x0010 /* b4: ping enable */
321#define CCPL 0x0004 /* b2: Enable control transfer complete */
322#define PID 0x0003 /* b1-0: Response PID */
323#define PID_STALL11 0x0003 /* STALL */
324#define PID_STALL 0x0002 /* STALL */
325#define PID_BUF 0x0001 /* BUF */
326#define PID_NAK 0x0000 /* NAK */
327
328/* Pipe Window Select Register */
329#define PIPENM 0x0007 /* b2-0: Pipe select */
330
331/* Pipe Configuration Register */
332#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
333#define R8A66597_ISO 0xC000 /* Isochronous */
334#define R8A66597_INT 0x8000 /* Interrupt */
335#define R8A66597_BULK 0x4000 /* Bulk */
336#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
337#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
338#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
339#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
340#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
341#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
342
343/* Pipe Buffer Configuration Register */
344#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
345#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
346#define PIPE0BUF 256
347#define PIPExBUF 64
348
349/* Pipe Maxpacket Size Register */
350#define MXPS 0x07FF /* b10-0: Maxpacket size */
351
352/* Pipe Cycle Configuration Register */
353#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
354#define IITV 0x0007 /* b2-0: Isochronous interval */
355
356/* Pipex Control Register */
357#define BSTS 0x8000 /* b15: Buffer status */
358#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
359#define CSCLR 0x2000 /* b13: complete-split status clear */
360#define CSSTS 0x1000 /* b12: complete-split status */
361#define ATREPM 0x0400 /* b10: Auto repeat mode */
362#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
363#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
364#define SQSET 0x0080 /* b7: Sequence toggle bit set */
365#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
366#define PBUSY 0x0020 /* b5: pipe busy */
367#define PID 0x0003 /* b1-0: Response PID */
368
369/* PIPExTRE */
370#define TRENB 0x0200 /* b9: Transaction counter enable */
371#define TRCLR 0x0100 /* b8: Transaction counter clear */
372
373/* PIPExTRN */
374#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
375
376/* DEVADDx */
377#define UPPHUB 0x7800
378#define HUBPORT 0x0700
379#define USBSPD 0x00C0
380#define RTPORT 0x0001
381
382#define R8A66597_MAX_NUM_PIPE 10
383#define R8A66597_BUF_BSIZE 8
384#define R8A66597_MAX_DEVICE 10
385#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
386#define R8A66597_MAX_ROOT_HUB 1
387#else
388#define R8A66597_MAX_ROOT_HUB 2
389#endif
390#define R8A66597_MAX_SAMPLING 5
391#define R8A66597_RH_POLL_TIME 10
392
393#define BULK_IN_PIPENUM 3
394#define BULK_IN_BUFNUM 8
395
396#define BULK_OUT_PIPENUM 4
397#define BULK_OUT_BUFNUM 40
398
399#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
400#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
401#define make_devsel(addr) (addr << 12)
402
403struct r8a66597 {
404 unsigned long reg;
405 unsigned short pipe_config; /* bit field */
406 unsigned short port_status;
407 unsigned short port_change;
408 u16 speed; /* HSMODE or FSMODE or LSMODE */
409 unsigned char rh_devnum;
410};
411
412static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
413{
414 return inw(r8a66597->reg + offset);
415}
416
417static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
418 unsigned long offset, void *buf,
419 int len)
420{
421 int i;
422#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
423 unsigned long fifoaddr = r8a66597->reg + offset;
424 unsigned long count;
425 unsigned long *p = buf;
426
427 count = len / 4;
428 for (i = 0; i < count; i++)
Nobuhiro Iwamatsu0b09f542011-07-11 11:03:47 +0900429 p[i] = inl(r8a66597->reg + offset);
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900430
431 if (len & 0x00000003) {
432 unsigned long tmp = inl(fifoaddr);
433 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
434 }
435#else
436 unsigned short *p = buf;
437
438 len = (len + 1) / 2;
439 for (i = 0; i < len; i++)
440 p[i] = inw(r8a66597->reg + offset);
441#endif
442}
443
444static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
445 unsigned long offset)
446{
447 outw(val, r8a66597->reg + offset);
448}
449
450static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
451 unsigned long offset, void *buf,
452 int len)
453{
454 int i;
455 unsigned long fifoaddr = r8a66597->reg + offset;
456#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
457 unsigned long count;
458 unsigned char *pb;
459 unsigned long *p = buf;
460
461 count = len / 4;
462 for (i = 0; i < count; i++)
463 outl(p[i], fifoaddr);
464
465 if (len & 0x00000003) {
466 pb = (unsigned char *)buf + count * 4;
467 for (i = 0; i < (len & 0x00000003); i++) {
468 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
469 outb(pb[i], fifoaddr + i);
470 else
471 outb(pb[i], fifoaddr + 3 - i);
472 }
473 }
474#else
475 int odd = len & 0x0001;
476 unsigned short *p = buf;
477
478 len = len / 2;
479 for (i = 0; i < len; i++)
480 outw(p[i], fifoaddr);
481
482 if (odd) {
483 unsigned char *pb = (unsigned char *)(buf + len);
484 outb(*pb, fifoaddr);
485 }
486#endif
487}
488
489static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
490 u16 val, u16 pat, unsigned long offset)
491{
492 u16 tmp;
493 tmp = r8a66597_read(r8a66597, offset);
494 tmp = tmp & (~pat);
495 tmp = tmp | val;
496 r8a66597_write(r8a66597, tmp, offset);
497}
498
499#define r8a66597_bclr(r8a66597, val, offset) \
500 r8a66597_mdfy(r8a66597, 0, val, offset)
501#define r8a66597_bset(r8a66597, val, offset) \
502 r8a66597_mdfy(r8a66597, val, 0, offset)
503
504static inline unsigned long get_syscfg_reg(int port)
505{
506 return port == 0 ? SYSCFG0 : SYSCFG1;
507}
508
509static inline unsigned long get_syssts_reg(int port)
510{
511 return port == 0 ? SYSSTS0 : SYSSTS1;
512}
513
514static inline unsigned long get_dvstctr_reg(int port)
515{
516 return port == 0 ? DVSTCTR0 : DVSTCTR1;
517}
518
519static inline unsigned long get_dmacfg_reg(int port)
520{
521 return port == 0 ? DMA0CFG : DMA1CFG;
522}
523
524static inline unsigned long get_intenb_reg(int port)
525{
526 return port == 0 ? INTENB1 : INTENB2;
527}
528
529static inline unsigned long get_intsts_reg(int port)
530{
531 return port == 0 ? INTSTS1 : INTSTS2;
532}
533
534static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
535{
536 unsigned long dvstctr_reg = get_dvstctr_reg(port);
537
538 return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
539}
540
541static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
542 int power)
543{
544 unsigned long dvstctr_reg = get_dvstctr_reg(port);
545
546 if (power)
547 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
548 else
549 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
550}
551
552#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
553#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
554#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
555#define get_devadd_addr(address) (DEVADD0 + address * 2)
556
557
558/* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */
559
560/* destination of request */
561#define RH_INTERFACE 0x01
562#define RH_ENDPOINT 0x02
563#define RH_OTHER 0x03
564
565#define RH_CLASS 0x20
566#define RH_VENDOR 0x40
567
568/* Requests: bRequest << 8 | bmRequestType */
569#define RH_GET_STATUS 0x0080
570#define RH_CLEAR_FEATURE 0x0100
571#define RH_SET_FEATURE 0x0300
572#define RH_SET_ADDRESS 0x0500
573#define RH_GET_DESCRIPTOR 0x0680
574#define RH_SET_DESCRIPTOR 0x0700
575#define RH_GET_CONFIGURATION 0x0880
576#define RH_SET_CONFIGURATION 0x0900
577#define RH_GET_STATE 0x0280
578#define RH_GET_INTERFACE 0x0A80
579#define RH_SET_INTERFACE 0x0B00
580#define RH_SYNC_FRAME 0x0C80
581/* Our Vendor Specific Request */
582#define RH_SET_EP 0x2000
583
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900584/* Hub port features */
585#define RH_PORT_CONNECTION 0x00
586#define RH_PORT_ENABLE 0x01
587#define RH_PORT_SUSPEND 0x02
588#define RH_PORT_OVER_CURRENT 0x03
589#define RH_PORT_RESET 0x04
590#define RH_PORT_POWER 0x08
591#define RH_PORT_LOW_SPEED 0x09
592
593#define RH_C_PORT_CONNECTION 0x10
594#define RH_C_PORT_ENABLE 0x11
595#define RH_C_PORT_SUSPEND 0x12
596#define RH_C_PORT_OVER_CURRENT 0x13
597#define RH_C_PORT_RESET 0x14
598
599/* Hub features */
600#define RH_C_HUB_LOCAL_POWER 0x00
601#define RH_C_HUB_OVER_CURRENT 0x01
602
603#define RH_DEVICE_REMOTE_WAKEUP 0x00
604#define RH_ENDPOINT_STALL 0x01
605
606#define RH_ACK 0x01
607#define RH_REQ_ERR -1
608#define RH_NACK 0x00
609
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900610/* OHCI ROOT HUB REGISTER MASKS */
611
612/* roothub.portstatus [i] bits */
613#define RH_PS_CCS 0x00000001 /* current connect status */
614#define RH_PS_PES 0x00000002 /* port enable status*/
615#define RH_PS_PSS 0x00000004 /* port suspend status */
616#define RH_PS_POCI 0x00000008 /* port over current indicator */
617#define RH_PS_PRS 0x00000010 /* port reset status */
618#define RH_PS_PPS 0x00000100 /* port power status */
619#define RH_PS_LSDA 0x00000200 /* low speed device attached */
620#define RH_PS_CSC 0x00010000 /* connect status change */
621#define RH_PS_PESC 0x00020000 /* port enable status change */
622#define RH_PS_PSSC 0x00040000 /* port suspend status change */
623#define RH_PS_OCIC 0x00080000 /* over current indicator change */
624#define RH_PS_PRSC 0x00100000 /* port reset status change */
625
626/* roothub.status bits */
627#define RH_HS_LPS 0x00000001 /* local power status */
628#define RH_HS_OCI 0x00000002 /* over current indicator */
629#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
630#define RH_HS_LPSC 0x00010000 /* local power status change */
631#define RH_HS_OCIC 0x00020000 /* over current indicator change */
632#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
633
634/* roothub.b masks */
635#define RH_B_DR 0x0000ffff /* device removable flags */
636#define RH_B_PPCM 0xffff0000 /* port power control mask */
637
638/* roothub.a masks */
639#define RH_A_NDP (0xff << 0) /* number of downstream ports */
640#define RH_A_PSM (1 << 8) /* power switching mode */
641#define RH_A_NPS (1 << 9) /* no power switching */
642#define RH_A_DT (1 << 10) /* device type (mbz) */
643#define RH_A_OCPM (1 << 11) /* over current protection mode */
644#define RH_A_NOCP (1 << 12) /* no over current protection */
645#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
646
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900647#endif /* __R8A66597_H__ */