| Paul Burton | b2b135d | 2016-09-21 11:18:53 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * MIPS Coherence Manager (CM) Register Definitions | ||||
| 3 | * | ||||
| 4 | * Copyright (c) 2016 Imagination Technologies Ltd. | ||||
| 5 | * | ||||
| 6 | * SPDX-License-Identifier: GPL-2.0+ | ||||
| 7 | */ | ||||
| 8 | #ifndef __MIPS_ASM_CM_H__ | ||||
| 9 | #define __MIPS_ASM_CM_H__ | ||||
| 10 | |||||
| 11 | /* Global Control Register (GCR) offsets */ | ||||
| 12 | #define GCR_BASE 0x0008 | ||||
| 13 | #define GCR_BASE_UPPER 0x000c | ||||
| 14 | #define GCR_REV 0x0030 | ||||
| 15 | |||||
| 16 | /* GCR_REV CM versions */ | ||||
| 17 | #define GCR_REV_CM3 0x0800 | ||||
| 18 | |||||
| 19 | #endif /* __MIPS_ASM_CM_H__ */ | ||||