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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Bill Richardson55ae10f2012-10-20 11:44:34 +00002/*
3 * Copyright (c) 2012 The Chromium OS Authors.
Bill Richardson55ae10f2012-10-20 11:44:34 +00004 */
5
6/*
7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
8 * through the PCI bus. Each PCI device has 256 bytes of configuration space,
9 * consisting of a standard header and a device-specific set of registers. PCI
10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
11 * other things). Within the PCI configuration space, the GPIOBASE register
12 * tells us where in the device's I/O region we can find more registers to
13 * actually access the GPIOs.
14 *
15 * PCI bus/device/function 0:1f:0 => PCI config registers
16 * PCI config register "GPIOBASE"
17 * PCI I/O space + [GPIOBASE] => start of GPIO registers
18 * GPIO registers => gpio pin function, direction, value
Bill Richardson57be9172012-10-20 11:44:36 +000019 *
20 *
21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
22 * ICH versions have more, but the decoding the matrix that describes them is
23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
24 * but they will ONLY work for certain unspecified chipsets because the offset
25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
26 * reserved or subject to arcane restrictions.
Bill Richardson55ae10f2012-10-20 11:44:34 +000027 */
28
29#include <common.h>
Simon Glass74141122014-10-10 07:49:18 -060030#include <dm.h>
31#include <errno.h>
32#include <fdtdec.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060033#include <log.h>
Bin Meng3ddc1c72016-02-01 01:40:47 -080034#include <pch.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000035#include <pci.h>
Simon Glass15cf75e2016-03-11 22:07:14 -070036#include <asm/cpu.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000037#include <asm/gpio.h>
38#include <asm/io.h>
Simon Glass1b4f25f2014-11-12 22:42:24 -070039#include <asm/pci.h>
Bill Richardson55ae10f2012-10-20 11:44:34 +000040
Simon Glass8b097912015-07-31 09:31:31 -060041DECLARE_GLOBAL_DATA_PTR;
42
Simon Glass74141122014-10-10 07:49:18 -060043#define GPIO_PER_BANK 32
44
Simon Glass74141122014-10-10 07:49:18 -060045struct ich6_bank_priv {
46 /* These are I/O addresses */
Bin Mengb71eec32014-12-17 15:50:38 +080047 uint16_t use_sel;
48 uint16_t io_sel;
49 uint16_t lvl;
Bin Meng770ee012017-05-07 19:52:29 -070050 u32 lvl_write_cache;
51 bool use_lvl_write_cache;
Bill Richardson57be9172012-10-20 11:44:36 +000052};
Bill Richardson55ae10f2012-10-20 11:44:34 +000053
Gabriel Huau5318f182015-05-25 22:27:37 -070054#define GPIO_USESEL_OFFSET(x) (x)
55#define GPIO_IOSEL_OFFSET(x) (x + 4)
56#define GPIO_LVL_OFFSET(x) (x + 8)
57
Bin Meng770ee012017-05-07 19:52:29 -070058static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset,
59 int value)
Gabriel Huau5318f182015-05-25 22:27:37 -070060{
61 u32 val;
62
Bin Meng770ee012017-05-07 19:52:29 -070063 if (bank->use_lvl_write_cache)
64 val = bank->lvl_write_cache;
65 else
66 val = inl(bank->lvl);
67
Gabriel Huau5318f182015-05-25 22:27:37 -070068 if (value)
69 val |= (1UL << offset);
70 else
71 val &= ~(1UL << offset);
Bin Meng770ee012017-05-07 19:52:29 -070072 outl(val, bank->lvl);
73 if (bank->use_lvl_write_cache)
74 bank->lvl_write_cache = val;
Gabriel Huau5318f182015-05-25 22:27:37 -070075
76 return 0;
77}
78
Gabriel Huau5318f182015-05-25 22:27:37 -070079static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
80{
81 u32 val;
82
83 if (!dir) {
84 val = inl(base);
85 val |= (1UL << offset);
86 outl(val, base);
87 } else {
88 val = inl(base);
89 val &= ~(1UL << offset);
90 outl(val, base);
91 }
92
93 return 0;
94}
95
Gabriel Huau5318f182015-05-25 22:27:37 -070096static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
97{
98 struct ich6_bank_platdata *plat = dev_get_platdata(dev);
Bin Meng3ddc1c72016-02-01 01:40:47 -080099 u32 gpiobase;
Gabriel Huau5318f182015-05-25 22:27:37 -0700100 int offset;
Bin Meng3ddc1c72016-02-01 01:40:47 -0800101 int ret;
Gabriel Huau5318f182015-05-25 22:27:37 -0700102
Bin Meng3ddc1c72016-02-01 01:40:47 -0800103 ret = pch_get_gpio_base(dev->parent, &gpiobase);
104 if (ret)
105 return ret;
106
Simon Glasse160f7d2017-01-17 16:52:55 -0700107 offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
Simon Glass74141122014-10-10 07:49:18 -0600108 if (offset == -1) {
109 debug("%s: Invalid register offset %d\n", __func__, offset);
110 return -EINVAL;
111 }
Simon Glassd6d50db2016-03-06 19:28:13 -0700112 plat->offset = offset;
Simon Glass74141122014-10-10 07:49:18 -0600113 plat->base_addr = gpiobase + offset;
Simon Glasse160f7d2017-01-17 16:52:55 -0700114 plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
Simon Glass74141122014-10-10 07:49:18 -0600115 "bank-name", NULL);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000116
Bill Richardson55ae10f2012-10-20 11:44:34 +0000117 return 0;
118}
119
Simon Glass1b4f25f2014-11-12 22:42:24 -0700120static int ich6_gpio_probe(struct udevice *dev)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000121{
Simon Glass74141122014-10-10 07:49:18 -0600122 struct ich6_bank_platdata *plat = dev_get_platdata(dev);
Simon Glasse564f052015-03-05 12:25:20 -0700123 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass74141122014-10-10 07:49:18 -0600124 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bin Meng770ee012017-05-07 19:52:29 -0700125 const void *prop;
Bin Meng27955732014-12-12 21:05:23 +0800126
Simon Glass74141122014-10-10 07:49:18 -0600127 uc_priv->gpio_count = GPIO_PER_BANK;
128 uc_priv->bank_name = plat->bank_name;
129 bank->use_sel = plat->base_addr;
130 bank->io_sel = plat->base_addr + 4;
131 bank->lvl = plat->base_addr + 8;
132
Simon Glassda409cc2017-05-17 17:18:09 -0600133 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
Bin Meng770ee012017-05-07 19:52:29 -0700134 "use-lvl-write-cache", NULL);
135 if (prop)
136 bank->use_lvl_write_cache = true;
137 else
138 bank->use_lvl_write_cache = false;
139 bank->lvl_write_cache = 0;
140
Simon Glass74141122014-10-10 07:49:18 -0600141 return 0;
142}
143
Simon Glass1b4f25f2014-11-12 22:42:24 -0700144static int ich6_gpio_request(struct udevice *dev, unsigned offset,
145 const char *label)
Simon Glass74141122014-10-10 07:49:18 -0600146{
147 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000148 u32 tmplong;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000149
150 /*
151 * Make sure that the GPIO pin we want isn't already in use for some
152 * built-in hardware function. We have to check this for every
153 * requested pin.
154 */
Simon Glass74141122014-10-10 07:49:18 -0600155 tmplong = inl(bank->use_sel);
156 if (!(tmplong & (1UL << offset))) {
Bill Richardson57be9172012-10-20 11:44:36 +0000157 debug("%s: gpio %d is reserved for internal use\n", __func__,
Simon Glass74141122014-10-10 07:49:18 -0600158 offset);
159 return -EPERM;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000160 }
161
Bill Richardson55ae10f2012-10-20 11:44:34 +0000162 return 0;
163}
164
Simon Glass74141122014-10-10 07:49:18 -0600165static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000166{
Simon Glass74141122014-10-10 07:49:18 -0600167 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson57be9172012-10-20 11:44:36 +0000168
Simon Glasse7cc0b62015-08-22 15:58:58 -0600169 return _ich6_gpio_set_direction(bank->io_sel, offset, 0);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000170}
171
Simon Glass74141122014-10-10 07:49:18 -0600172static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
173 int value)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000174{
Gabriel Huau5318f182015-05-25 22:27:37 -0700175 int ret;
Simon Glass74141122014-10-10 07:49:18 -0600176 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000177
Simon Glasse7cc0b62015-08-22 15:58:58 -0600178 ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);
Gabriel Huau5318f182015-05-25 22:27:37 -0700179 if (ret)
180 return ret;
Axel Lin0a547452014-12-07 12:48:27 +0800181
Bin Meng770ee012017-05-07 19:52:29 -0700182 return _ich6_gpio_set_value(bank, offset, value);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000183}
184
Simon Glass74141122014-10-10 07:49:18 -0600185static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000186{
Simon Glass74141122014-10-10 07:49:18 -0600187 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000188 u32 tmplong;
Bill Richardson57be9172012-10-20 11:44:36 +0000189 int r;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000190
Simon Glass74141122014-10-10 07:49:18 -0600191 tmplong = inl(bank->lvl);
Bin Meng770ee012017-05-07 19:52:29 -0700192 if (bank->use_lvl_write_cache)
193 tmplong |= bank->lvl_write_cache;
Simon Glass74141122014-10-10 07:49:18 -0600194 r = (tmplong & (1UL << offset)) ? 1 : 0;
Bill Richardson57be9172012-10-20 11:44:36 +0000195 return r;
Bill Richardson55ae10f2012-10-20 11:44:34 +0000196}
197
Simon Glass74141122014-10-10 07:49:18 -0600198static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
199 int value)
Bill Richardson55ae10f2012-10-20 11:44:34 +0000200{
Simon Glass74141122014-10-10 07:49:18 -0600201 struct ich6_bank_priv *bank = dev_get_priv(dev);
Bin Meng770ee012017-05-07 19:52:29 -0700202 return _ich6_gpio_set_value(bank, offset, value);
Bill Richardson55ae10f2012-10-20 11:44:34 +0000203}
Simon Glass74141122014-10-10 07:49:18 -0600204
205static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
206{
207 struct ich6_bank_priv *bank = dev_get_priv(dev);
208 u32 mask = 1UL << offset;
209
210 if (!(inl(bank->use_sel) & mask))
211 return GPIOF_FUNC;
212 if (inl(bank->io_sel) & mask)
213 return GPIOF_INPUT;
214 else
215 return GPIOF_OUTPUT;
216}
217
218static const struct dm_gpio_ops gpio_ich6_ops = {
219 .request = ich6_gpio_request,
220 .direction_input = ich6_gpio_direction_input,
221 .direction_output = ich6_gpio_direction_output,
222 .get_value = ich6_gpio_get_value,
223 .set_value = ich6_gpio_set_value,
224 .get_function = ich6_gpio_get_function,
225};
226
227static const struct udevice_id intel_ich6_gpio_ids[] = {
228 { .compatible = "intel,ich6-gpio" },
229 { }
230};
231
232U_BOOT_DRIVER(gpio_ich6) = {
233 .name = "gpio_ich6",
234 .id = UCLASS_GPIO,
235 .of_match = intel_ich6_gpio_ids,
236 .ops = &gpio_ich6_ops,
237 .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
238 .probe = ich6_gpio_probe,
239 .priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
240 .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
241};