blob: 95d70bc6e7161466d87013d2535b7cd82e956932 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +09002/*
3 * Configuation settings for the sh7757lcr board
4 *
5 * Copyright (C) 2011 Renesas Solutions Corp.
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +09006 */
7
8#ifndef __SH7757LCR_H
9#define __SH7757LCR_H
10
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090011#define CONFIG_CPU_SH7757 1
Nobuhiro Iwamatsu3ed81642011-10-31 13:16:02 +090012#define CONFIG_SH7757LCR_DDR_ECC 1
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090013
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020014#define CONFIG_DISPLAY_BOARDINFO
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090015#undef CONFIG_SHOW_BOOT_PROGRESS
16
17/* MEMORY */
18#define SH7757LCR_SDRAM_BASE (0x80000000)
19#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
20#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
21#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
22
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090023#define CONFIG_SYS_PBSIZE 256
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090024#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
25
26/* SCIF */
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090027#define CONFIG_CONS_SCIF2 1
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090028
29#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
30#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
31 224 * 1024 * 1024)
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090032#undef CONFIG_SYS_MEMTEST_SCRATCH
33#undef CONFIG_SYS_LOADS_BAUD_CHANGE
34
35#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
36#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
37#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
38 (128 + 16) * 1024 * 1024)
39
40#define CONFIG_SYS_MONITOR_BASE 0x00000000
41#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
42#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
43#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
44
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090045/* Ether */
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090046#define CONFIG_SH_ETHER_USE_PORT 0
47#define CONFIG_SH_ETHER_PHY_ADDR 1
48#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
Yoshihiro Shimoda0c2a37a2011-10-11 18:11:03 +090049#define CONFIG_BITBANGMII
50#define CONFIG_BITBANGMII_MULTI
Nobuhiro Iwamatsua80a6612012-05-16 10:23:21 +090051#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090052
53#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
54#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
55#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
56#define SH7757LCR_ETHERNET_MAC_SIZE 17
57#define SH7757LCR_ETHERNET_NUM_CH 2
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090058
59/* Gigabit Ether */
60#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
61
62/* SPI */
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090063#define CONFIG_SH_SPI_BASE 0xfe002000
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090064
Yoshihiro Shimoda566f63d2012-03-05 20:11:12 +000065/* MMCIF */
Yoshihiro Shimoda566f63d2012-03-05 20:11:12 +000066#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
67#define CONFIG_SH_MMCIF_CLK 48000000
68
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090069/* SH7757 board */
70#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
71#define SH7757LCR_GRA_OFFSET 0x1f000000
72#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
73#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
74#define SH7757LCR_PCIEBRG_ADDR 0x00090000
75#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
76
77/* ENV setting */
78#define CONFIG_ENV_IS_EMBEDDED
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090079#define CONFIG_ENV_SECT_SIZE (64 * 1024)
80#define CONFIG_ENV_ADDR (0x00080000)
81#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
82#define CONFIG_ENV_OVERWRITE 1
83#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
84#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
85#define CONFIG_EXTRA_ENV_SETTINGS \
86 "netboot=bootp; bootm\0"
87
88/* Board Clock */
89#define CONFIG_SYS_CLK_FREQ 48000000
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090090#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
91#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090092#define CONFIG_SYS_TMU_CLK_DIV 4
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090093#endif /* __SH7757LCR_H */