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wdenk04a85b32004-04-15 18:22:41 +00001/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
wdenkc26e4542004-04-18 10:13:26 +000032#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
33#error Unsupported CONFIG_NETPHONE version
34#endif
35
wdenk04a85b32004-04-15 18:22:41 +000036/*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40
41#define CONFIG_MPC870 1 /* This is a MPC885 CPU */
42#define CONFIG_NETPHONE 1 /* ...on a NetPhone board */
43
44#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45#undef CONFIG_8xx_CONS_SMC2
46#undef CONFIG_8xx_CONS_NONE
47
48#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
49
50/* #define CONFIG_XIN 10000000 */
51#define CONFIG_XIN 50000000
wdenk79fa88f2004-06-07 23:46:25 +000052/* #define MPC8XX_HZ 120000000 */
53#define MPC8XX_HZ 66666666
wdenk04a85b32004-04-15 18:22:41 +000054
55#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
56
57#if 0
58#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
59#else
60#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61#endif
62
63#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
64
65#define CONFIG_PREBOOT "echo;"
66
67#undef CONFIG_BOOTARGS
68#define CONFIG_BOOTCOMMAND \
69 "tftpboot; " \
wdenk79fa88f2004-06-07 23:46:25 +000070 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk04a85b32004-04-15 18:22:41 +000072 "bootm"
73
74#define CONFIG_AUTOSCRIPT
75#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
76#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
77
78#undef CONFIG_WATCHDOG /* watchdog disabled */
79
80#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
81
82#define CONFIG_STATUS_LED 1 /* Status LED enabled */
83#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
84
Jon Loeliger7be044e2007-07-09 21:24:19 -050085/*
86 * BOOTP options
87 */
88#define CONFIG_BOOTP_SUBNETMASK
89#define CONFIG_BOOTP_GATEWAY
90#define CONFIG_BOOTP_HOSTNAME
91#define CONFIG_BOOTP_BOOTPATH
92#define CONFIG_BOOTP_BOOTFILESIZE
93#define CONFIG_BOOTP_NISDOMAIN
wdenk04a85b32004-04-15 18:22:41 +000094
95#undef CONFIG_MAC_PARTITION
96#undef CONFIG_DOS_PARTITION
97
98#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
99
100#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
101#define FEC_ENET 1 /* eth.c needs it that way... */
102#undef CFG_DISCOVER_PHY
103#define CONFIG_MII 1
104#define CONFIG_RMII 1 /* use RMII interface */
105
106#define CONFIG_ETHER_ON_FEC1 1
107#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
108#define CONFIG_FEC1_PHY_NORXERR 1
109
110#define CONFIG_ETHER_ON_FEC2 1
111#define CONFIG_FEC2_PHY 4
112#define CONFIG_FEC2_PHY_NORXERR 1
113
114#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
115
Jon Loeligere18a1062007-07-08 14:21:43 -0500116
117/*
118 * Command line configuration.
119 */
120#include <config_cmd_default.h>
121
122#define CONFIG_CMD_NAND
123#define CONFIG_CMD_DHCP
124#define CONFIG_CMD_PING
125#define CONFIG_CMD_MII
126#define CONFIG_CMD_CDP
127
wdenk04a85b32004-04-15 18:22:41 +0000128
129#define CONFIG_BOARD_EARLY_INIT_F 1
130#define CONFIG_MISC_INIT_R
131
wdenk04a85b32004-04-15 18:22:41 +0000132/*
133 * Miscellaneous configurable options
134 */
135#define CFG_LONGHELP /* undef to save memory */
136#define CFG_PROMPT "=> " /* Monitor Command Prompt */
137
138#define CFG_HUSH_PARSER 1
139#define CFG_PROMPT_HUSH_PS2 "> "
140
Jon Loeligere18a1062007-07-08 14:21:43 -0500141#if defined(CONFIG_CMD_KGDB)
wdenk04a85b32004-04-15 18:22:41 +0000142#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
143#else
144#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
145#endif
146#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
147#define CFG_MAXARGS 16 /* max number of command args */
148#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
149
150#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
151#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
152
153#define CFG_LOAD_ADDR 0x100000 /* default load address */
154
155#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
156
157#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
158
159/*
160 * Low Level Configuration Settings
161 * (address mappings, register initial values, etc.)
162 * You should know what you are doing if you make changes here.
163 */
164/*-----------------------------------------------------------------------
165 * Internal Memory Mapped Register
166 */
167#define CFG_IMMR 0xFF000000
168
169/*-----------------------------------------------------------------------
170 * Definitions for initial stack pointer and data area (in DPRAM)
171 */
172#define CFG_INIT_RAM_ADDR CFG_IMMR
173#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
174#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
175#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
176#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
177
178/*-----------------------------------------------------------------------
179 * Start addresses for the final memory configuration
180 * (Set up by the startup code)
181 * Please note that CFG_SDRAM_BASE _must_ start at 0
182 */
183#define CFG_SDRAM_BASE 0x00000000
184#define CFG_FLASH_BASE 0x40000000
185#if defined(DEBUG)
186#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
187#else
188#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
189#endif
190#define CFG_MONITOR_BASE CFG_FLASH_BASE
191#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkc26e4542004-04-18 10:13:26 +0000192#if CONFIG_NETPHONE_VERSION == 2
193#define CFG_FLASH_BASE4 0x40080000
194#endif
195
196#define CFG_RESET_ADDRESS 0x80000000
wdenk04a85b32004-04-15 18:22:41 +0000197
198/*
199 * For booting Linux, the board info and command line data
200 * have to be in the first 8 MB of memory, since this is
201 * the maximum mapped by the Linux kernel during initialization.
202 */
203#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
204
205/*-----------------------------------------------------------------------
206 * FLASH organization
207 */
wdenkc26e4542004-04-18 10:13:26 +0000208#if CONFIG_NETPHONE_VERSION == 1
wdenk04a85b32004-04-15 18:22:41 +0000209#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenkc26e4542004-04-18 10:13:26 +0000210#elif CONFIG_NETPHONE_VERSION == 2
211#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
212#endif
wdenk04a85b32004-04-15 18:22:41 +0000213#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
214
215#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
216#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
217
218#define CFG_ENV_IS_IN_FLASH 1
219#define CFG_ENV_SECT_SIZE 0x10000
220
221#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
222#define CFG_ENV_OFFSET 0
223#define CFG_ENV_SIZE 0x4000
224
225#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
226#define CFG_ENV_OFFSET_REDUND 0
227#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
228
229/*-----------------------------------------------------------------------
230 * Cache Configuration
231 */
232#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligere18a1062007-07-08 14:21:43 -0500233#if defined(CONFIG_CMD_KGDB)
wdenk04a85b32004-04-15 18:22:41 +0000234#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
235#endif
236
237/*-----------------------------------------------------------------------
238 * SYPCR - System Protection Control 11-9
239 * SYPCR can only be written once after reset!
240 *-----------------------------------------------------------------------
241 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
242 */
243#if defined(CONFIG_WATCHDOG)
244#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
245 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
246#else
247#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
248#endif
249
250/*-----------------------------------------------------------------------
251 * SIUMCR - SIU Module Configuration 11-6
252 *-----------------------------------------------------------------------
253 * PCMCIA config., multi-function pin tri-state
254 */
255#ifndef CONFIG_CAN_DRIVER
256#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
257#else /* we must activate GPL5 in the SIUMCR for CAN */
258#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
259#endif /* CONFIG_CAN_DRIVER */
260
261/*-----------------------------------------------------------------------
262 * TBSCR - Time Base Status and Control 11-26
263 *-----------------------------------------------------------------------
264 * Clear Reference Interrupt Status, Timebase freezing enabled
265 */
266#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
267
268/*-----------------------------------------------------------------------
269 * RTCSC - Real-Time Clock Status and Control Register 11-27
270 *-----------------------------------------------------------------------
271 */
272#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
273
274/*-----------------------------------------------------------------------
275 * PISCR - Periodic Interrupt Status and Control 11-31
276 *-----------------------------------------------------------------------
277 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
278 */
279#define CFG_PISCR (PISCR_PS | PISCR_PITF)
280
281/*-----------------------------------------------------------------------
282 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
283 *-----------------------------------------------------------------------
284 * Reset PLL lock status sticky bit, timer expired status bit and timer
285 * interrupt status bit
286 *
287 */
288
289#if CONFIG_XIN == 10000000
290
291#if MPC8XX_HZ == 120000000
292#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
293 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
294 PLPRCR_TEXPS)
295#elif MPC8XX_HZ == 100000000
296#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
297 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
298 PLPRCR_TEXPS)
299#elif MPC8XX_HZ == 50000000
300#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
301 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
302 PLPRCR_TEXPS)
303#elif MPC8XX_HZ == 25000000
304#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
305 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
306 PLPRCR_TEXPS)
307#elif MPC8XX_HZ == 40000000
308#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
309 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
310 PLPRCR_TEXPS)
311#elif MPC8XX_HZ == 75000000
312#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
313 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
314 PLPRCR_TEXPS)
315#else
316#error unsupported CPU freq for XIN = 10MHz
317#endif
318
319#elif CONFIG_XIN == 50000000
320
321#if MPC8XX_HZ == 120000000
322#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
323 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
324 PLPRCR_TEXPS)
325#elif MPC8XX_HZ == 100000000
326#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
327 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
328 PLPRCR_TEXPS)
wdenkc26e4542004-04-18 10:13:26 +0000329#elif MPC8XX_HZ == 66666666
330#define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
331 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
332 PLPRCR_TEXPS)
wdenk04a85b32004-04-15 18:22:41 +0000333#else
334#error unsupported CPU freq for XIN = 50MHz
335#endif
336
337#else
338
339#error unsupported XIN freq
340#endif
341
342
343/*
344 *-----------------------------------------------------------------------
345 * SCCR - System Clock and reset Control Register 15-27
346 *-----------------------------------------------------------------------
347 * Set clock output, timebase and RTC source and divider,
348 * power management and some other internal clocks
wdenk79fa88f2004-06-07 23:46:25 +0000349 *
350 * Note: When TBS == 0 the timebase is independent of current cpu clock.
wdenk04a85b32004-04-15 18:22:41 +0000351 */
352
353#define SCCR_MASK SCCR_EBDF11
354#if MPC8XX_HZ > 66666666
wdenk79fa88f2004-06-07 23:46:25 +0000355#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
wdenk04a85b32004-04-15 18:22:41 +0000356 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
357 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
358 SCCR_DFALCD00 | SCCR_EBDF01)
359#else
wdenk79fa88f2004-06-07 23:46:25 +0000360#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
wdenk04a85b32004-04-15 18:22:41 +0000361 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
362 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
363 SCCR_DFALCD00)
364#endif
365
366/*-----------------------------------------------------------------------
367 *
368 *-----------------------------------------------------------------------
369 *
370 */
371/*#define CFG_DER 0x2002000F*/
372#define CFG_DER 0
373
374/*
375 * Init Memory Controller:
376 *
377 * BR0/1 and OR0/1 (FLASH)
378 */
379
380#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
381
382/* used to re-map FLASH both when starting from SRAM or FLASH:
383 * restrict access enough to keep SRAM working (if any)
384 * but not too much to meddle with FLASH accesses
385 */
386#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
387#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
388
389/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
390#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
391
392#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
393#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
394#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
395
wdenkc26e4542004-04-18 10:13:26 +0000396#if CONFIG_NETPHONE_VERSION == 2
397
398#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
399
400#define CFG_OR4_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
401#define CFG_OR4_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
402#define CFG_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
403
404#endif
405
wdenk04a85b32004-04-15 18:22:41 +0000406/*
407 * BR3 and OR3 (SDRAM)
408 *
409 */
410#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
411#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
412
413/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
414#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
415
416#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
417#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
418
419/*
420 * Memory Periodic Timer Prescaler
421 */
422
423/*
424 * Memory Periodic Timer Prescaler
425 *
426 * The Divider for PTA (refresh timer) configuration is based on an
427 * example SDRAM configuration (64 MBit, one bank). The adjustment to
428 * the number of chip selects (NCS) and the actually needed refresh
429 * rate is done by setting MPTPR.
430 *
431 * PTA is calculated from
432 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
433 *
434 * gclk CPU clock (not bus clock!)
435 * Trefresh Refresh cycle * 4 (four word bursts used)
436 *
437 * 4096 Rows from SDRAM example configuration
438 * 1000 factor s -> ms
439 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
440 * 4 Number of refresh cycles per period
441 * 64 Refresh cycle in ms per number of rows
442 * --------------------------------------------
443 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
444 *
445 * 50 MHz => 50.000.000 / Divider = 98
446 * 66 Mhz => 66.000.000 / Divider = 129
447 * 80 Mhz => 80.000.000 / Divider = 156
448 */
449
450#define CFG_MAMR_PTA 234
451
452/*
453 * For 16 MBit, refresh rates could be 31.3 us
454 * (= 64 ms / 2K = 125 / quad bursts).
455 * For a simpler initialization, 15.6 us is used instead.
456 *
457 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
458 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
459 */
460#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
461#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
462
463/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
464#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
465#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
466
467/*
468 * MAMR settings for SDRAM
469 */
470
471/* 8 column SDRAM */
472#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
473 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
474 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
475
476/* 9 column SDRAM */
477#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
478 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
479 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
480
481/*
482 * Internal Definitions
483 *
484 * Boot Flags
485 */
486#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
487#define BOOTFLAG_WARM 0x02 /* Software reboot */
488
489#define CONFIG_ARTOS /* include ARTOS support */
490
491#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
492
493/****************************************************************/
494
495#define DSP_SIZE 0x00010000 /* 64K */
496#define NAND_SIZE 0x00010000 /* 64K */
wdenk04a85b32004-04-15 18:22:41 +0000497
498#define DSP_BASE 0xF1000000
499#define NAND_BASE 0xF1010000
wdenk04a85b32004-04-15 18:22:41 +0000500
501/****************************************************************/
502
503/* NAND */
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100504#define CFG_NAND_LEGACY
wdenk04a85b32004-04-15 18:22:41 +0000505#define CFG_NAND_BASE NAND_BASE
506#define CONFIG_MTD_NAND_ECC_JFFS2
wdenk79fa88f2004-06-07 23:46:25 +0000507#define CONFIG_MTD_NAND_VERIFY_WRITE
508#define CONFIG_MTD_NAND_UNSAFE
wdenk04a85b32004-04-15 18:22:41 +0000509
510#define CFG_MAX_NAND_DEVICE 1
511
512#define SECTORSIZE 512
513#define ADDR_COLUMN 1
514#define ADDR_PAGE 2
515#define ADDR_COLUMN_PAGE 3
516#define NAND_ChipID_UNKNOWN 0x00
517#define NAND_MAX_FLOORS 1
518#define NAND_MAX_CHIPS 1
519
520/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
521#define NAND_DISABLE_CE(nand) \
522 do { \
523 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
524 } while(0)
525
526#define NAND_ENABLE_CE(nand) \
527 do { \
528 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
529 } while(0)
530
531#define NAND_CTL_CLRALE(nandptr) \
532 do { \
533 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
534 } while(0)
535
536#define NAND_CTL_SETALE(nandptr) \
537 do { \
538 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
539 } while(0)
540
541#define NAND_CTL_CLRCLE(nandptr) \
542 do { \
543 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
544 } while(0)
545
546#define NAND_CTL_SETCLE(nandptr) \
547 do { \
548 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
549 } while(0)
550
wdenkc26e4542004-04-18 10:13:26 +0000551#if CONFIG_NETPHONE_VERSION == 1
wdenk04a85b32004-04-15 18:22:41 +0000552#define NAND_WAIT_READY(nand) \
553 do { \
wdenkc26e4542004-04-18 10:13:26 +0000554 int _tries = 0; \
wdenk04a85b32004-04-15 18:22:41 +0000555 while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
wdenkc26e4542004-04-18 10:13:26 +0000556 if (++_tries > 100000) \
557 break; \
wdenk04a85b32004-04-15 18:22:41 +0000558 } while (0)
wdenkc26e4542004-04-18 10:13:26 +0000559#elif CONFIG_NETPHONE_VERSION == 2
560#define NAND_WAIT_READY(nand) \
561 do { \
562 int _tries = 0; \
563 while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
564 if (++_tries > 100000) \
565 break; \
566 } while (0)
567#endif
wdenk04a85b32004-04-15 18:22:41 +0000568
569#define WRITE_NAND_COMMAND(d, adr) \
570 do { \
571 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
572 } while(0)
573
574#define WRITE_NAND_ADDRESS(d, adr) \
575 do { \
576 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
577 } while(0)
578
579#define WRITE_NAND(d, adr) \
580 do { \
581 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
582 } while(0)
583
584#define READ_NAND(adr) \
585 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
586
587/*****************************************************************************/
588
wdenk79fa88f2004-06-07 23:46:25 +0000589#define CFG_DIRECT_FLASH_TFTP
590#define CFG_DIRECT_NAND_TFTP
591
592/*****************************************************************************/
593
wdenkc26e4542004-04-18 10:13:26 +0000594#if CONFIG_NETPHONE_VERSION == 1
wdenk04a85b32004-04-15 18:22:41 +0000595#define STATUS_LED_BIT 0x00000008 /* bit 28 */
wdenkc26e4542004-04-18 10:13:26 +0000596#elif CONFIG_NETPHONE_VERSION == 2
597#define STATUS_LED_BIT 0x00000080 /* bit 24 */
598#endif
599
wdenk04a85b32004-04-15 18:22:41 +0000600#define STATUS_LED_PERIOD (CFG_HZ / 2)
601#define STATUS_LED_STATE STATUS_LED_BLINKING
602
603#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
604#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
605
606#ifndef __ASSEMBLY__
607
608/* LEDs */
609
610/* led_id_t is unsigned int mask */
611typedef unsigned int led_id_t;
612
613#define __led_toggle(_msk) \
614 do { \
615 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
616 } while(0)
617
618#define __led_set(_msk, _st) \
619 do { \
620 if ((_st)) \
621 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
622 else \
623 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
624 } while(0)
625
626#define __led_init(msk, st) __led_set(msk, st)
627
628#endif
629
630/***********************************************************************************************************
631
wdenkc26e4542004-04-18 10:13:26 +0000632 ----------------------------------------------------------------------------------------------
633
634 (V1) version 1 of the board
635 (V2) version 2 of the board
636
637 ----------------------------------------------------------------------------------------------
638
wdenk04a85b32004-04-15 18:22:41 +0000639 Pin definitions:
640
641 +------+----------------+--------+------------------------------------------------------------
642 | # | Name | Type | Comment
643 +------+----------------+--------+------------------------------------------------------------
644 | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select
645 | PA7 | DSP_INT | Output | DSP interrupt
646 | PA10 | DSP_RESET | Output | DSP reset
647 | PA14 | USBOE | Output | USB (1)
648 | PA15 | USBRXD | Output | USB (1)
649 | PB19 | BT_RTS | Output | Bluetooth (0)
650 | PB23 | BT_CTS | Output | Bluetooth (0)
651 | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select
652 | PB27 | SPICS_DISP | Output | Display chip select
653 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
654 | PB29 | SPI_TXD | Output | SPI Data Tx
655 | PB30 | SPI_CLK | Output | SPI Clock
656 | PC10 | DISPA0 | Output | Display A0
657 | PC11 | BACKLIGHT | Output | Display backlit
wdenkc26e4542004-04-18 10:13:26 +0000658 | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
659 | | IO_RESET | Output | (V2) General I/O reset
660 | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
661 | | HOOK | Input | (V2) Hook input interrupt
662 | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
663 | | F_RY_BY | Input | (V2) NAND F_RY_BY
wdenk04a85b32004-04-15 18:22:41 +0000664 | PE17 | F_ALE | Output | NAND F_ALE
665 | PE18 | F_CLE | Output | NAND F_CLE
666 | PE20 | F_CE | Output | NAND F_CE
wdenkc26e4542004-04-18 10:13:26 +0000667 | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
668 | | LED | Output | (V2) LED
wdenk04a85b32004-04-15 18:22:41 +0000669 | PE27 | SPICS_ER | Output | External serial register CS
wdenkc26e4542004-04-18 10:13:26 +0000670 | PE28 | LEDIO1 | Output | (V1) LED
671 | | BKBR1 | Input | (V2) Keyboard input scan
672 | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
673 | | BKBR2 | Input | (V2) Keyboard input scan
674 | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
675 | | BKBR3 | Input | (V2) Keyboard input scan
676 | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
677 | | BKBR4 | Input | (V2) Keyboard input scan
wdenk04a85b32004-04-15 18:22:41 +0000678 +------+----------------+--------+---------------------------------------------------
679
wdenkc26e4542004-04-18 10:13:26 +0000680 ----------------------------------------------------------------------------------------------
681
682 Serial register input:
683
684 +------+----------------+------------------------------------------------------------
685 | # | Name | Comment
686 +------+----------------+------------------------------------------------------------
wdenk6e592382004-04-18 17:39:38 +0000687 | 0 | BKBR1 | (V1) Keyboard input scan
688 | 1 | BKBR3 | (V1) Keyboard input scan
689 | 2 | BKBR4 | (V1) Keyboard input scan
690 | 3 | BKBR2 | (V1) Keyboard input scan
691 | 4 | HOOK | (V1) Hook switch
wdenkc26e4542004-04-18 10:13:26 +0000692 | 5 | BT_LINK | (V1) Bluetooth link status
693 | 6 | HOST_WAKE | (V1) Bluetooth host wake up
694 | 7 | OK_ETH | (V1) Cisco inline power OK status
695 +------+----------------+------------------------------------------------------------
696
697 ----------------------------------------------------------------------------------------------
698
699 Serial register output:
700
701 +------+----------------+------------------------------------------------------------
702 | # | Name | Comment
703 +------+----------------+------------------------------------------------------------
wdenk6e592382004-04-18 17:39:38 +0000704 | 0 | KEY1 | Keyboard output scan
705 | 1 | KEY2 | Keyboard output scan
706 | 2 | KEY3 | Keyboard output scan
707 | 3 | KEY4 | Keyboard output scan
708 | 4 | KEY5 | Keyboard output scan
709 | 5 | KEY6 | Keyboard output scan
710 | 6 | KEY7 | Keyboard output scan
wdenkc26e4542004-04-18 10:13:26 +0000711 | 7 | BT_WAKE | Bluetooth wake up
712 +------+----------------+------------------------------------------------------------
713
714 ----------------------------------------------------------------------------------------------
715
wdenk04a85b32004-04-15 18:22:41 +0000716 Chip selects:
717
718 +------+----------------+------------------------------------------------------------
719 | # | Name | Comment
720 +------+----------------+------------------------------------------------------------
721 | CS0 | CS0 | Boot flash
722 | CS1 | CS_FLASH | NAND flash
723 | CS2 | CS_DSP | DSP
724 | CS3 | DCS_DRAM | DRAM
wdenkc26e4542004-04-18 10:13:26 +0000725 | CS4 | CS_FLASH2 | (V2) 2nd flash
wdenk04a85b32004-04-15 18:22:41 +0000726 +------+----------------+------------------------------------------------------------
727
wdenkc26e4542004-04-18 10:13:26 +0000728 ----------------------------------------------------------------------------------------------
729
wdenk04a85b32004-04-15 18:22:41 +0000730 Interrupts:
731
732 +------+----------------+------------------------------------------------------------
733 | # | Name | Comment
734 +------+----------------+------------------------------------------------------------
735 | IRQ1 | IRQ_DSP | DSP interrupt
736 | IRQ3 | S_INTER | DUSLIC ???
737 | IRQ4 | F_RY_BY | NAND
738 | IRQ7 | IRQ_MAX | MAX 3100 interrupt
739 +------+----------------+------------------------------------------------------------
740
wdenkc26e4542004-04-18 10:13:26 +0000741 ----------------------------------------------------------------------------------------------
742
wdenk04a85b32004-04-15 18:22:41 +0000743 Interrupts on PCMCIA pins:
744
745 +------+----------------+------------------------------------------------------------
746 | # | Name | Comment
747 +------+----------------+------------------------------------------------------------
748 | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface
749 | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
750 | IP_A2| RMII1_MDINT | PHY interrupt for #1
751 | IP_A3| RMII2_MDINT | PHY interrupt for #2
wdenkc26e4542004-04-18 10:13:26 +0000752 | IP_A5| HOST_WAKE | (V2) Bluetooth host wake
753 | IP_A6| OK_ETH | (V2) Cisco inline power OK
wdenk04a85b32004-04-15 18:22:41 +0000754 +------+----------------+------------------------------------------------------------
755
756*************************************************************************************************/
757
758#define CONFIG_SED156X 1 /* use SED156X */
759#define CONFIG_SED156X_PG12864Q 1 /* type of display used */
760
761/* serial interfacing macros */
762
763#define SED156X_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
764#define SED156X_SPI_RXD_MASK 0x00000008
765
766#define SED156X_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
767#define SED156X_SPI_TXD_MASK 0x00000004
768
769#define SED156X_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
770#define SED156X_SPI_CLK_MASK 0x00000002
771
772#define SED156X_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
773#define SED156X_CS_MASK 0x00000010
774
775#define SED156X_A0_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
776#define SED156X_A0_MASK 0x0020
777
778/*************************************************************************************************/
779
780#define CFG_CONSOLE_IS_IN_ENV 1
781#define CFG_CONSOLE_OVERWRITE_ROUTINE 1
782#define CFG_CONSOLE_ENV_OVERWRITE 1
783
784/*************************************************************************************************/
785
786/* use board specific hardware */
787#undef CONFIG_WATCHDOG /* watchdog disabled */
788#define CONFIG_HW_WATCHDOG
789#define CONFIG_SHOW_ACTIVITY
790
791/*************************************************************************************************/
792
793/* phone console configuration */
794
795#define PHONE_CONSOLE_POLL_HZ (CFG_HZ/200) /* poll every 5ms */
796
797/*************************************************************************************************/
798
799#define CONFIG_CDP_DEVICE_ID 20
800#define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */
801#define CONFIG_CDP_PORT_ID "eth%d"
802#define CONFIG_CDP_CAPABILITIES 0x00000010
803#define CONFIG_CDP_VERSION "u-boot" " " __DATE__ " " __TIME__
804#define CONFIG_CDP_PLATFORM "Intracom NetPhone"
805#define CONFIG_CDP_TRIGGER 0x20020001
806#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
807#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */
808
809/*************************************************************************************************/
810
811#define CONFIG_AUTO_COMPLETE 1
812
813/*************************************************************************************************/
814
wdenkc26e4542004-04-18 10:13:26 +0000815#define CONFIG_CRC32_VERIFY 1
816
817/*************************************************************************************************/
818
819#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
820
821/*************************************************************************************************/
wdenk04a85b32004-04-15 18:22:41 +0000822#endif /* __CONFIG_H */