blob: 4496871ff3e07c2e1ddf18587ca1bd8b2a1955de [file] [log] [blame]
Wang Huan550e3dc2014-09-05 13:52:44 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10#include <config_cmd_default.h>
11
12#define CONFIG_LS102XA
13
14#define CONFIG_SYS_GENERIC_BOARD
15
16#define CONFIG_DISPLAY_CPUINFO
17#define CONFIG_DISPLAY_BOARDINFO
18
19#define CONFIG_SKIP_LOWLEVEL_INIT
20#define CONFIG_BOARD_EARLY_INIT_F
21
22/*
23 * Size of malloc() pool
24 */
25#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
26
27#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
28#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
29
30/*
31 * Generic Timer Definitions
32 */
33#define GENERIC_TIMER_CLK 12500000
34
35#ifndef __ASSEMBLY__
36unsigned long get_board_sys_clk(void);
37unsigned long get_board_ddr_clk(void);
38#endif
39
40#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
41#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
42
Alison Wang86949c22014-12-03 15:00:47 +080043#ifdef CONFIG_RAMBOOT_PBL
44#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
45#endif
46
47#ifdef CONFIG_SD_BOOT
48#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
49#define CONFIG_SPL_FRAMEWORK
50#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
51#define CONFIG_SPL_LIBCOMMON_SUPPORT
52#define CONFIG_SPL_LIBGENERIC_SUPPORT
53#define CONFIG_SPL_ENV_SUPPORT
54#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
55#define CONFIG_SPL_I2C_SUPPORT
56#define CONFIG_SPL_WATCHDOG_SUPPORT
57#define CONFIG_SPL_SERIAL_SUPPORT
58#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
59#define CONFIG_SPL_MMC_SUPPORT
60#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
61#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
62
63#define CONFIG_SPL_TEXT_BASE 0x10000000
64#define CONFIG_SPL_MAX_SIZE 0x1a000
65#define CONFIG_SPL_STACK 0x1001d000
66#define CONFIG_SPL_PAD_TO 0x1c000
67#define CONFIG_SYS_TEXT_BASE 0x82000000
68
69#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
70#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
71#define CONFIG_SPL_BSS_START_ADDR 0x80100000
72#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
73#define CONFIG_SYS_MONITOR_LEN 0x80000
74#endif
75
Wang Huan550e3dc2014-09-05 13:52:44 +080076#ifndef CONFIG_SYS_TEXT_BASE
77#define CONFIG_SYS_TEXT_BASE 0x67f80000
78#endif
79
80#define CONFIG_NR_DRAM_BANKS 1
81
82#define CONFIG_DDR_SPD
83#define SPD_EEPROM_ADDRESS 0x51
84#define CONFIG_SYS_SPD_BUS_NUM 0
Wang Huan550e3dc2014-09-05 13:52:44 +080085
86#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
York Sunc7eae7f2014-09-11 13:32:07 -070087#ifndef CONFIG_SYS_FSL_DDR4
Wang Huan550e3dc2014-09-05 13:52:44 +080088#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
York Sunc7eae7f2014-09-11 13:32:07 -070089#define CONFIG_SYS_DDR_RAW_TIMING
90#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080091#define CONFIG_DIMM_SLOTS_PER_CTLR 1
92#define CONFIG_CHIP_SELECTS_PER_CTRL 4
93
94#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
95#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
96
97#define CONFIG_DDR_ECC
98#ifdef CONFIG_DDR_ECC
99#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
100#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
101#endif
102
103#define CONFIG_SYS_HAS_SERDES
104
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530105#define CONFIG_FSL_CAAM /* Enable CAAM */
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800106
Alison Wang4c59ab92014-12-09 17:37:49 +0800107#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
108 !defined(CONFIG_QSPI_BOOT)
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800109#define CONFIG_U_QE
110#endif
111
Wang Huan550e3dc2014-09-05 13:52:44 +0800112/*
113 * IFC Definitions
114 */
115#define CONFIG_FSL_IFC
116#define CONFIG_SYS_FLASH_BASE 0x60000000
117#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
118
119#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
120#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
121 CSPR_PORT_SIZE_16 | \
122 CSPR_MSEL_NOR | \
123 CSPR_V)
124#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
125#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
126 + 0x8000000) | \
127 CSPR_PORT_SIZE_16 | \
128 CSPR_MSEL_NOR | \
129 CSPR_V)
130#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
131
132#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
133 CSOR_NOR_TRHZ_80)
134#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
135 FTIM0_NOR_TEADC(0x5) | \
136 FTIM0_NOR_TEAHC(0x5))
137#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
138 FTIM1_NOR_TRAD_NOR(0x1a) | \
139 FTIM1_NOR_TSEQRAD_NOR(0x13))
140#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
141 FTIM2_NOR_TCH(0x4) | \
142 FTIM2_NOR_TWPH(0xe) | \
143 FTIM2_NOR_TWP(0x1c))
144#define CONFIG_SYS_NOR_FTIM3 0
145
146#define CONFIG_FLASH_CFI_DRIVER
147#define CONFIG_SYS_FLASH_CFI
148#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
149#define CONFIG_SYS_FLASH_QUIET_TEST
150#define CONFIG_FLASH_SHOW_PROGRESS 45
151#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Yuan Yao272c5262014-10-17 15:26:34 +0800152#define CONFIG_SYS_WRITE_SWAPPED_DATA
Wang Huan550e3dc2014-09-05 13:52:44 +0800153
154#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
155#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
156#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
157#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
158
159#define CONFIG_SYS_FLASH_EMPTY_INFO
160#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
161 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
162
163/*
164 * NAND Flash Definitions
165 */
166#define CONFIG_NAND_FSL_IFC
167
168#define CONFIG_SYS_NAND_BASE 0x7e800000
169#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
170
171#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
172
173#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
174 | CSPR_PORT_SIZE_8 \
175 | CSPR_MSEL_NAND \
176 | CSPR_V)
177#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
178#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
179 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
180 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
181 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
182 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
183 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
184 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
185
186#define CONFIG_SYS_NAND_ONFI_DETECTION
187
188#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
189 FTIM0_NAND_TWP(0x18) | \
190 FTIM0_NAND_TWCHT(0x7) | \
191 FTIM0_NAND_TWH(0xa))
192#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
193 FTIM1_NAND_TWBE(0x39) | \
194 FTIM1_NAND_TRR(0xe) | \
195 FTIM1_NAND_TRP(0x18))
196#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
197 FTIM2_NAND_TREH(0xa) | \
198 FTIM2_NAND_TWHRE(0x1e))
199#define CONFIG_SYS_NAND_FTIM3 0x0
200
201#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
202#define CONFIG_SYS_MAX_NAND_DEVICE 1
203#define CONFIG_MTD_NAND_VERIFY_WRITE
204#define CONFIG_CMD_NAND
205
206#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
207
208/*
209 * QIXIS Definitions
210 */
211#define CONFIG_FSL_QIXIS
212
213#ifdef CONFIG_FSL_QIXIS
214#define QIXIS_BASE 0x7fb00000
215#define QIXIS_BASE_PHYS QIXIS_BASE
216#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
217#define QIXIS_LBMAP_SWITCH 6
218#define QIXIS_LBMAP_MASK 0x0f
219#define QIXIS_LBMAP_SHIFT 0
220#define QIXIS_LBMAP_DFLTBANK 0x00
221#define QIXIS_LBMAP_ALTBANK 0x04
222#define QIXIS_RST_CTL_RESET 0x44
223#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
224#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
225#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
226
227#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
228#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
229 CSPR_PORT_SIZE_8 | \
230 CSPR_MSEL_GPCM | \
231 CSPR_V)
232#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
233#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
234 CSOR_NOR_NOR_MODE_AVD_NOR | \
235 CSOR_NOR_TRHZ_80)
236
237/*
238 * QIXIS Timing parameters for IFC GPCM
239 */
240#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
241 FTIM0_GPCM_TEADC(0xe) | \
242 FTIM0_GPCM_TEAHC(0xe))
243#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
244 FTIM1_GPCM_TRAD(0x1f))
245#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
246 FTIM2_GPCM_TCH(0xe) | \
247 FTIM2_GPCM_TWP(0xf0))
248#define CONFIG_SYS_FPGA_FTIM3 0x0
249#endif
250
251#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
252#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
253#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
254#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
255#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
256#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
257#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
258#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
259#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
260#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
261#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
262#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
263#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
264#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
265#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
266#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
267#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
268#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
269#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
270#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
271#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
272#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
273#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
274#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
275#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
276#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
277#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
278#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
279#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
280#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
281#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
282#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
283
284/*
285 * Serial Port
286 */
287#define CONFIG_CONS_INDEX 1
288#define CONFIG_SYS_NS16550
289#define CONFIG_SYS_NS16550_SERIAL
290#define CONFIG_SYS_NS16550_REG_SIZE 1
291#define CONFIG_SYS_NS16550_CLK get_serial_clock()
292
293#define CONFIG_BAUDRATE 115200
294
295/*
296 * I2C
297 */
298#define CONFIG_CMD_I2C
299#define CONFIG_SYS_I2C
300#define CONFIG_SYS_I2C_MXC
301
302/*
303 * I2C bus multiplexer
304 */
305#define I2C_MUX_PCA_ADDR_PRI 0x77
306#define I2C_MUX_CH_DEFAULT 0x8
307
308/*
309 * MMC
310 */
311#define CONFIG_MMC
312#define CONFIG_CMD_MMC
313#define CONFIG_FSL_ESDHC
314#define CONFIG_GENERIC_MMC
315
Alison Wang8251ed22014-12-09 17:37:34 +0800316#define CONFIG_CMD_FAT
317#define CONFIG_DOS_PARTITION
318
Wang Huan550e3dc2014-09-05 13:52:44 +0800319/*
Nikhil Badola8776cb22014-10-17 11:37:25 +0530320 * USB
321 */
322#define CONFIG_HAS_FSL_DR_USB
323
324#ifdef CONFIG_HAS_FSL_DR_USB
325#define CONFIG_USB_EHCI
326
327#ifdef CONFIG_USB_EHCI
328#define CONFIG_CMD_USB
329#define CONFIG_USB_STORAGE
330#define CONFIG_USB_EHCI_FSL
331#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
332#define CONFIG_CMD_EXT2
333#endif
334#endif
335
336/*
Wang Huan550e3dc2014-09-05 13:52:44 +0800337 * eTSEC
338 */
339#define CONFIG_TSEC_ENET
340
341#ifdef CONFIG_TSEC_ENET
342#define CONFIG_MII
343#define CONFIG_MII_DEFAULT_TSEC 3
344#define CONFIG_TSEC1 1
345#define CONFIG_TSEC1_NAME "eTSEC1"
346#define CONFIG_TSEC2 1
347#define CONFIG_TSEC2_NAME "eTSEC2"
348#define CONFIG_TSEC3 1
349#define CONFIG_TSEC3_NAME "eTSEC3"
350
351#define TSEC1_PHY_ADDR 1
352#define TSEC2_PHY_ADDR 2
353#define TSEC3_PHY_ADDR 3
354
355#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
356#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
357#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
358
359#define TSEC1_PHYIDX 0
360#define TSEC2_PHYIDX 0
361#define TSEC3_PHYIDX 0
362
363#define CONFIG_ETHPRIME "eTSEC1"
364
365#define CONFIG_PHY_GIGE
366#define CONFIG_PHYLIB
367#define CONFIG_PHY_REALTEK
368
369#define CONFIG_HAS_ETH0
370#define CONFIG_HAS_ETH1
371#define CONFIG_HAS_ETH2
372
373#define CONFIG_FSL_SGMII_RISER 1
374#define SGMII_RISER_PHY_OFFSET 0x1b
375
376#ifdef CONFIG_FSL_SGMII_RISER
377#define CONFIG_SYS_TBIPA_VALUE 8
378#endif
379
380#endif
Minghuan Lianda419022014-10-31 13:43:44 +0800381
382/* PCIe */
383#define CONFIG_PCI /* Enable PCI/PCIE */
384#define CONFIG_PCIE1 /* PCIE controler 1 */
385#define CONFIG_PCIE2 /* PCIE controler 2 */
386#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
387#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
388
Wang Huan550e3dc2014-09-05 13:52:44 +0800389#define CONFIG_CMD_PING
390#define CONFIG_CMD_DHCP
391#define CONFIG_CMD_MII
392#define CONFIG_CMD_NET
393
394#define CONFIG_CMDLINE_TAG
395#define CONFIG_CMDLINE_EDITING
Alison Wang86949c22014-12-03 15:00:47 +0800396
Wang Huan550e3dc2014-09-05 13:52:44 +0800397#define CONFIG_CMD_IMLS
398
399#define CONFIG_HWCONFIG
400#define HWCONFIG_BUFFER_SIZE 128
401
402#define CONFIG_BOOTDELAY 3
403
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800404#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
405
Wang Huan550e3dc2014-09-05 13:52:44 +0800406#define CONFIG_EXTRA_ENV_SETTINGS \
407 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
408 "fdt_high=0xcfffffff\0" \
409 "initrd_high=0xcfffffff\0" \
410 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
411
412/*
413 * Miscellaneous configurable options
414 */
415#define CONFIG_SYS_LONGHELP /* undef to save memory */
416#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
417#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Wang Huan550e3dc2014-09-05 13:52:44 +0800418#define CONFIG_AUTO_COMPLETE
419#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
420#define CONFIG_SYS_PBSIZE \
421 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
422#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
423#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
424
425#define CONFIG_CMD_ENV_EXISTS
426#define CONFIG_CMD_GREPENV
427#define CONFIG_CMD_MEMINFO
428#define CONFIG_CMD_MEMTEST
429#define CONFIG_SYS_MEMTEST_START 0x80000000
430#define CONFIG_SYS_MEMTEST_END 0x9fffffff
431
432#define CONFIG_SYS_LOAD_ADDR 0x82000000
Wang Huan550e3dc2014-09-05 13:52:44 +0800433
434/*
435 * Stack sizes
436 * The stack sizes are set up in start.S using the settings below
437 */
438#define CONFIG_STACKSIZE (30 * 1024)
439
440#define CONFIG_SYS_INIT_SP_OFFSET \
441 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
442#define CONFIG_SYS_INIT_SP_ADDR \
443 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
444
Alison Wang86949c22014-12-03 15:00:47 +0800445#ifdef CONFIG_SPL_BUILD
446#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
447#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800448#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Alison Wang86949c22014-12-03 15:00:47 +0800449#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800450
451/*
452 * Environment
453 */
454#define CONFIG_ENV_OVERWRITE
455
Alison Wang86949c22014-12-03 15:00:47 +0800456#if defined(CONFIG_SD_BOOT)
457#define CONFIG_ENV_OFFSET 0x100000
458#define CONFIG_ENV_IS_IN_MMC
459#define CONFIG_SYS_MMC_ENV_DEV 0
460#define CONFIG_ENV_SIZE 0x2000
461#else
Wang Huan550e3dc2014-09-05 13:52:44 +0800462#define CONFIG_ENV_IS_IN_FLASH
463#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
464#define CONFIG_ENV_SIZE 0x2000
465#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
Alison Wang86949c22014-12-03 15:00:47 +0800466#endif
Wang Huan550e3dc2014-09-05 13:52:44 +0800467
468#define CONFIG_OF_LIBFDT
469#define CONFIG_OF_BOARD_SETUP
470#define CONFIG_CMD_BOOTZ
471
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530472#define CONFIG_MISC_INIT_R
473
474/* Hash command with SHA acceleration supported in hardware */
475#define CONFIG_CMD_HASH
476#define CONFIG_SHA_HW_ACCEL
477
Ruchika Guptaba474022014-10-07 15:48:47 +0530478#ifdef CONFIG_SECURE_BOOT
479#define CONFIG_CMD_BLOB
480#endif
481
Wang Huan550e3dc2014-09-05 13:52:44 +0800482#endif