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wdenk2f001a32002-09-06 19:36:05 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2002
6 * Gregory E. Allen, gallen@arlut.utexas.edu
7 * Applied Research Laboratories, The University of Texas at Austin
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <mpc824x.h>
30#include <asm/processor.h>
31
32/* ------------------------------------------------------------------------- */
33/* NOTE: This describes the proper use of this file.
34 *
35 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency on
36 * PCI_SYNC_IN .
37 *
38 * CONFIG_PLL_PCI_TO_MEM_MULTIPLIER is only required on MPC8240
39 * boards. It should be defined as the PCI to Memory Multiplier as
40 * documented in the MPC8240 Hardware Specs.
41 *
42 * Other mpc824x boards don't need CONFIG_PLL_PCI_TO_MEM_MULTIPLIER
43 * because they can determine it from the PCR.
44 *
45 * Gary Milliorn <gary.milliorn@motorola.com> (who should know since
46 * he designed the Sandpoint) told us that the PCR is not in all revs
47 * of the MPC8240 CPU, so it's not guaranteeable and we cannot do
48 * away with CONFIG_PLL_PCI_TO_MEM_MULTIPLIER altogether.
49 */
50/* ------------------------------------------------------------------------- */
51
52/* This gives the PCI to Memory multiplier times 10 */
53/* The index is the value of PLL_CFG[0:4] */
54/* This is documented in the MPC8240/5 Hardware Specs */
55
56short pll_pci_to_mem_multiplier[] = {
57#if defined(CONFIG_MPC8240)
58 30, 30, 10, 10, 20, 10, 0, 10,
59 10, 0, 20, 0, 20, 0, 20, 0,
60 30, 0, 15, 0, 20, 0, 20, 0,
61 25, 0, 10, 0, 15, 15, 0, 0,
62#elif defined(CONFIG_MPC8245)
63 30, 30, 10, 10, 20, 10, 10, 10,
wdenkfc3e2162003-10-08 22:33:00 +000064 10, 20, 20, 15, 20, 15, 20, 30,
65 30, 40, 15, 40, 20, 25, 20, 40,
wdenk2f001a32002-09-06 19:36:05 +000066 25, 20, 10, 20, 15, 15, 15, 0,
67#else
68#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
69#endif
70};
71
72#define CU824_PLL_STATE_REG 0xFE80002F
73#define PCR 0x800000E2
74
75/* ------------------------------------------------------------------------- */
76
77/* compute the memory bus clock frequency */
78ulong get_bus_freq (ulong dummy)
79{
80 unsigned char pll_cfg;
81#if defined(CONFIG_MPC8240) && !defined(CONFIG_CU824)
82 return (CONFIG_SYS_CLK_FREQ) * (CONFIG_PLL_PCI_TO_MEM_MULTIPLIER);
83#elif defined(CONFIG_CU824)
84 pll_cfg = *(volatile unsigned char *) (CU824_PLL_STATE_REG);
85 pll_cfg &= 0x1f;
86#else
87 CONFIG_READ_BYTE(PCR, pll_cfg);
88 pll_cfg = (pll_cfg >> 3) & 0x1f;
89#endif
90 return ((CONFIG_SYS_CLK_FREQ) * pll_pci_to_mem_multiplier[pll_cfg] + 5) / 10;
91}
92
93
94/* ------------------------------------------------------------------------- */
95
96/* This gives the Memory to CPU Core multiplier times 10 */
97/* The index is the value of PLLRATIO in HID1 */
98/* This is documented in the MPC8240 Hardware Specs */
99/* This is not documented for MPC8245 ? FIXME */
100short pllratio_to_factor[] = {
101 0, 0, 0, 10, 20, 20, 25, 45,
102 30, 0, 0, 0, 0, 0, 0, 0,
103 0, 0, 0, 10, 0, 0, 0, 45,
104 30, 0, 40, 0, 0, 0, 35, 0,
105};
106
107/* compute the CPU and memory bus clock frequencies */
108int get_clocks (void)
109{
110 DECLARE_GLOBAL_DATA_PTR;
111
112 uint hid1 = mfspr(HID1);
113 hid1 = (hid1 >> (32-5)) & 0x1f;
114 gd->cpu_clk = (pllratio_to_factor[hid1] * get_bus_freq(0) + 5)
115 / 10;
116 gd->bus_clk = get_bus_freq(0);
117 return (0);
118}