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wdenk71f95112003-06-15 22:40:42 +00001/*
2 * (C) Copyright 2003
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include <common.h>
26#include <mmc.h>
27#include <asm/errno.h>
28#include <asm/arch/hardware.h>
wdenk7205e402003-09-10 22:30:53 +000029#include <part.h>
wdenk71f95112003-06-15 22:40:42 +000030
31#ifdef CONFIG_MMC
32
33extern int
wdenk7205e402003-09-10 22:30:53 +000034fat_register_device(block_dev_desc_t *dev_desc, int part_no);
35
36static block_dev_desc_t mmc_dev;
37
38block_dev_desc_t * mmc_get_dev(int dev)
39{
40 return ((block_dev_desc_t *)&mmc_dev);
41}
wdenk71f95112003-06-15 22:40:42 +000042
wdenk8bde7f72003-06-27 21:31:46 +000043/*
wdenk71f95112003-06-15 22:40:42 +000044 * FIXME needs to read cid and csd info to determine block size
45 * and other parameters
46 */
47static uchar mmc_buf[MMC_BLOCK_SIZE];
48static mmc_csd_t mmc_csd;
49static int mmc_ready = 0;
50
51
wdenk8bde7f72003-06-27 21:31:46 +000052static uchar *
wdenk71f95112003-06-15 22:40:42 +000053/****************************************************/
54mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
55/****************************************************/
56{
57 static uchar resp[20];
58 ulong status;
59 int words, i;
60
61 debug("mmc_cmd %x %x %x %x\n", cmd, argh, argl, cmdat);
62 MMC_STRPCL = MMC_STRPCL_STOP_CLK;
63 MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF;
64 while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF));
wdenk8bde7f72003-06-27 21:31:46 +000065 MMC_CMD = cmd;
wdenk71f95112003-06-15 22:40:42 +000066 MMC_ARGH = argh;
67 MMC_ARGL = argl;
68 MMC_CMDAT = cmdat;
69 MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES;
70 MMC_STRPCL = MMC_STRPCL_START_CLK;
71 while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES));
72
73 status = MMC_STAT;
74 debug("MMC status %x\n", status);
wdenk20787e22005-04-06 00:04:16 +000075 if (status & MMC_STAT_TIME_OUT_RESPONSE) {
wdenk71f95112003-06-15 22:40:42 +000076 return 0;
77 }
78
wdenk20787e22005-04-06 00:04:16 +000079 switch (cmdat & 0x3) {
wdenk71f95112003-06-15 22:40:42 +000080 case MMC_CMDAT_R1:
81 case MMC_CMDAT_R3:
wdenk8bde7f72003-06-27 21:31:46 +000082 words = 3;
wdenk71f95112003-06-15 22:40:42 +000083 break;
84
85 case MMC_CMDAT_R2:
wdenk8bde7f72003-06-27 21:31:46 +000086 words = 8;
wdenk71f95112003-06-15 22:40:42 +000087 break;
88
89 default:
90 return 0;
91 }
wdenk20787e22005-04-06 00:04:16 +000092 for (i = words-1; i >= 0; i--) {
wdenk71f95112003-06-15 22:40:42 +000093 ulong res_fifo = MMC_RES;
94 int offset = i << 1;
95
96 resp[offset] = ((uchar *)&res_fifo)[0];
97 resp[offset+1] = ((uchar *)&res_fifo)[1];
98 }
99#ifdef MMC_DEBUG
wdenk20787e22005-04-06 00:04:16 +0000100 for (i=0; i<words*2; i += 2) {
wdenk71f95112003-06-15 22:40:42 +0000101 printf("MMC resp[%d] = %02x\n", i, resp[i]);
102 printf("MMC resp[%d] = %02x\n", i+1, resp[i+1]);
103 }
104#endif
105 return resp;
106}
107
108int
109/****************************************************/
110mmc_block_read(uchar *dst, ulong src, ulong len)
111/****************************************************/
112{
113 uchar *resp;
114 ushort argh, argl;
115 ulong status;
116
wdenk20787e22005-04-06 00:04:16 +0000117 if (len == 0) {
wdenk71f95112003-06-15 22:40:42 +0000118 return 0;
119 }
120
121 debug("mmc_block_rd dst %lx src %lx len %d\n", (ulong)dst, src, len);
122
123 argh = len >> 16;
124 argl = len & 0xffff;
125
126 /* set block len */
127 resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1);
128
129 /* send read command */
130 argh = src >> 16;
131 argl = src & 0xffff;
132 MMC_STRPCL = MMC_STRPCL_STOP_CLK;
133 MMC_RDTO = 0xffff;
134 MMC_NOB = 1;
135 MMC_BLKLEN = len;
wdenk8bde7f72003-06-27 21:31:46 +0000136 resp = mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl,
wdenk71f95112003-06-15 22:40:42 +0000137 MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN);
138
wdenk8bde7f72003-06-27 21:31:46 +0000139
wdenk71f95112003-06-15 22:40:42 +0000140 MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
wdenk20787e22005-04-06 00:04:16 +0000141 while (len) {
142 if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) {
143#ifdef CONFIG_PXA27X
144 int i;
145 for (i=min(len,32); i; i--) {
146 *dst++ = * ((volatile uchar *) &MMC_RXFIFO);
147 len--;
148 }
149#else
wdenk71f95112003-06-15 22:40:42 +0000150 *dst++ = MMC_RXFIFO;
151 len--;
wdenk20787e22005-04-06 00:04:16 +0000152#endif
wdenk71f95112003-06-15 22:40:42 +0000153 }
154 status = MMC_STAT;
wdenk20787e22005-04-06 00:04:16 +0000155 if (status & MMC_STAT_ERRORS) {
wdenk71f95112003-06-15 22:40:42 +0000156 printf("MMC_STAT error %lx\n", status);
157 return -1;
158 }
159 }
160 MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
161 while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE));
162 status = MMC_STAT;
wdenk20787e22005-04-06 00:04:16 +0000163 if (status & MMC_STAT_ERRORS) {
wdenk71f95112003-06-15 22:40:42 +0000164 printf("MMC_STAT error %lx\n", status);
165 return -1;
166 }
167 return 0;
168}
169
170int
171/****************************************************/
172mmc_block_write(ulong dst, uchar *src, int len)
173/****************************************************/
174{
175 uchar *resp;
176 ushort argh, argl;
177 ulong status;
178
wdenk20787e22005-04-06 00:04:16 +0000179 if (len == 0) {
wdenk71f95112003-06-15 22:40:42 +0000180 return 0;
181 }
182
183 debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong)src, len);
184
185 argh = len >> 16;
186 argl = len & 0xffff;
187
188 /* set block len */
189 resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1);
190
191 /* send write command */
192 argh = dst >> 16;
193 argl = dst & 0xffff;
194 MMC_STRPCL = MMC_STRPCL_STOP_CLK;
195 MMC_NOB = 1;
196 MMC_BLKLEN = len;
wdenk8bde7f72003-06-27 21:31:46 +0000197 resp = mmc_cmd(MMC_CMD_WRITE_BLOCK, argh, argl,
wdenk71f95112003-06-15 22:40:42 +0000198 MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN);
wdenk8bde7f72003-06-27 21:31:46 +0000199
wdenk71f95112003-06-15 22:40:42 +0000200 MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ;
wdenk20787e22005-04-06 00:04:16 +0000201 while (len) {
202 if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) {
wdenk71f95112003-06-15 22:40:42 +0000203 int i, bytes = min(32,len);
204
wdenk20787e22005-04-06 00:04:16 +0000205 for (i=0; i<bytes; i++) {
wdenk71f95112003-06-15 22:40:42 +0000206 MMC_TXFIFO = *src++;
207 }
wdenk20787e22005-04-06 00:04:16 +0000208 if (bytes < 32) {
wdenk71f95112003-06-15 22:40:42 +0000209 MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL;
210 }
211 len -= bytes;
212 }
213 status = MMC_STAT;
wdenk20787e22005-04-06 00:04:16 +0000214 if (status & MMC_STAT_ERRORS) {
wdenk71f95112003-06-15 22:40:42 +0000215 printf("MMC_STAT error %lx\n", status);
216 return -1;
217 }
218 }
219 MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
220 while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE));
221 MMC_I_MASK = ~MMC_I_MASK_PRG_DONE;
222 while (!(MMC_I_REG & MMC_I_REG_PRG_DONE));
223 status = MMC_STAT;
wdenk20787e22005-04-06 00:04:16 +0000224 if (status & MMC_STAT_ERRORS) {
wdenk71f95112003-06-15 22:40:42 +0000225 printf("MMC_STAT error %lx\n", status);
226 return -1;
227 }
228 return 0;
229}
230
231
232int
233/****************************************************/
234mmc_read(ulong src, uchar *dst, int size)
235/****************************************************/
236{
237 ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
238 ulong mmc_block_size, mmc_block_address;
239
wdenk20787e22005-04-06 00:04:16 +0000240 if (size == 0) {
wdenk71f95112003-06-15 22:40:42 +0000241 return 0;
242 }
243
wdenk20787e22005-04-06 00:04:16 +0000244 if (!mmc_ready) {
wdenk71f95112003-06-15 22:40:42 +0000245 printf("Please initial the MMC first\n");
246 return -1;
247 }
248
249 mmc_block_size = MMC_BLOCK_SIZE;
250 mmc_block_address = ~(mmc_block_size - 1);
251
252 src -= CFG_MMC_BASE;
253 end = src + size;
254 part_start = ~mmc_block_address & src;
255 part_end = ~mmc_block_address & end;
256 aligned_start = mmc_block_address & src;
257 aligned_end = mmc_block_address & end;
258
259 /* all block aligned accesses */
260 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
261 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000262 if (part_start) {
wdenk71f95112003-06-15 22:40:42 +0000263 part_len = mmc_block_size - part_start;
264 debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
265 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000266 if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
wdenk71f95112003-06-15 22:40:42 +0000267 return -1;
268 }
269 memcpy(dst, mmc_buf+part_start, part_len);
270 dst += part_len;
271 src += part_len;
272 }
273 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
274 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000275 for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
wdenk71f95112003-06-15 22:40:42 +0000276 debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
277 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000278 if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) {
wdenk71f95112003-06-15 22:40:42 +0000279 return -1;
280 }
281 }
282 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
283 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000284 if (part_end && src < end) {
wdenk71f95112003-06-15 22:40:42 +0000285 debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
286 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000287 if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
wdenk71f95112003-06-15 22:40:42 +0000288 return -1;
289 }
290 memcpy(dst, mmc_buf, part_end);
291 }
292 return 0;
293}
294
295int
296/****************************************************/
297mmc_write(uchar *src, ulong dst, int size)
298/****************************************************/
299{
300 ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
301 ulong mmc_block_size, mmc_block_address;
302
wdenk20787e22005-04-06 00:04:16 +0000303 if (size == 0) {
wdenk71f95112003-06-15 22:40:42 +0000304 return 0;
305 }
306
wdenk20787e22005-04-06 00:04:16 +0000307 if (!mmc_ready) {
wdenk71f95112003-06-15 22:40:42 +0000308 printf("Please initial the MMC first\n");
309 return -1;
310 }
311
312 mmc_block_size = MMC_BLOCK_SIZE;
313 mmc_block_address = ~(mmc_block_size - 1);
314
315 dst -= CFG_MMC_BASE;
316 end = dst + size;
317 part_start = ~mmc_block_address & dst;
318 part_end = ~mmc_block_address & end;
319 aligned_start = mmc_block_address & dst;
320 aligned_end = mmc_block_address & end;
321
322 /* all block aligned accesses */
323 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
324 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000325 if (part_start) {
wdenk71f95112003-06-15 22:40:42 +0000326 part_len = mmc_block_size - part_start;
327 debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
328 (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000329 if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
wdenk71f95112003-06-15 22:40:42 +0000330 return -1;
331 }
332 memcpy(mmc_buf+part_start, src, part_len);
wdenk20787e22005-04-06 00:04:16 +0000333 if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) {
wdenk71f95112003-06-15 22:40:42 +0000334 return -1;
335 }
336 dst += part_len;
337 src += part_len;
338 }
339 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
340 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000341 for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
wdenk71f95112003-06-15 22:40:42 +0000342 debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
343 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000344 if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) {
wdenk71f95112003-06-15 22:40:42 +0000345 return -1;
346 }
347 }
348 debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
349 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000350 if (part_end && dst < end) {
wdenk71f95112003-06-15 22:40:42 +0000351 debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
352 src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
wdenk20787e22005-04-06 00:04:16 +0000353 if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
wdenk71f95112003-06-15 22:40:42 +0000354 return -1;
355 }
356 memcpy(mmc_buf, src, part_end);
wdenk20787e22005-04-06 00:04:16 +0000357 if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
wdenk71f95112003-06-15 22:40:42 +0000358 return -1;
359 }
360 }
361 return 0;
362}
363
wdenk7205e402003-09-10 22:30:53 +0000364ulong
wdenk71f95112003-06-15 22:40:42 +0000365/****************************************************/
wdenk7205e402003-09-10 22:30:53 +0000366mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst)
wdenk71f95112003-06-15 22:40:42 +0000367/****************************************************/
368{
369 int mmc_block_size = MMC_BLOCK_SIZE;
370 ulong src = blknr * mmc_block_size + CFG_MMC_BASE;
371
372 mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size);
373 return blkcnt;
374}
375
376int
377/****************************************************/
378mmc_init(int verbose)
379/****************************************************/
380{
381 int retries, rc = -ENODEV;
382 uchar *resp;
383
384#ifdef CONFIG_LUBBOCK
385 set_GPIO_mode( GPIO6_MMCCLK_MD );
386 set_GPIO_mode( GPIO8_MMCCS0_MD );
387#endif
388 CKEN |= CKEN12_MMC; /* enable MMC unit clock */
wdenk20787e22005-04-06 00:04:16 +0000389#if defined(CONFIG_ADSVIX)
390 /* turn on the power */
391 GPCR(114) = GPIO_bit(114);
392 udelay(1000);
393#endif
wdenk71f95112003-06-15 22:40:42 +0000394
395 mmc_csd.c_size = 0;
396
397 MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
wdenk8bde7f72003-06-27 21:31:46 +0000398 MMC_RESTO = MMC_RES_TO_MAX;
wdenk71f95112003-06-15 22:40:42 +0000399 MMC_SPI = MMC_SPI_DISABLE;
400
401 /* reset */
402 retries = 10;
403 resp = mmc_cmd(0, 0, 0, 0);
404 resp = mmc_cmd(1, 0x00ff, 0xc000, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3);
wdenk20787e22005-04-06 00:04:16 +0000405 while (retries-- && resp && !(resp[4] & 0x80)) {
wdenk71f95112003-06-15 22:40:42 +0000406 debug("resp %x %x\n", resp[0], resp[1]);
wdenk20787e22005-04-06 00:04:16 +0000407#ifdef CONFIG_PXA27X
408 udelay(10000);
409#else
wdenk71f95112003-06-15 22:40:42 +0000410 udelay(50);
wdenk20787e22005-04-06 00:04:16 +0000411#endif
wdenk71f95112003-06-15 22:40:42 +0000412 resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3);
413 }
414
415 /* try to get card id */
416 resp = mmc_cmd(2, 0, 0, MMC_CMDAT_R2);
wdenk20787e22005-04-06 00:04:16 +0000417 if (resp) {
wdenk71f95112003-06-15 22:40:42 +0000418 /* TODO configure mmc driver depending on card attributes */
419 mmc_cid_t *cid = (mmc_cid_t *)resp;
wdenk20787e22005-04-06 00:04:16 +0000420 if (verbose) {
wdenk71f95112003-06-15 22:40:42 +0000421 printf("MMC found. Card desciption is:\n");
wdenk8bde7f72003-06-27 21:31:46 +0000422 printf("Manufacturer ID = %02x%02x%02x\n",
wdenk71f95112003-06-15 22:40:42 +0000423 cid->id[0], cid->id[1], cid->id[2]);
424 printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev);
425 cid->hwrev = cid->fwrev = 0; /* null terminate string */
426 printf("Product Name = %s\n",cid->name);
wdenk8bde7f72003-06-27 21:31:46 +0000427 printf("Serial Number = %02x%02x%02x\n",
wdenk71f95112003-06-15 22:40:42 +0000428 cid->sn[0], cid->sn[1], cid->sn[2]);
429 printf("Month = %d\n",cid->month);
430 printf("Year = %d\n",1997 + cid->year);
431 }
wdenk7205e402003-09-10 22:30:53 +0000432 /* fill in device description */
433 mmc_dev.if_type = IF_TYPE_MMC;
wdenk20787e22005-04-06 00:04:16 +0000434 mmc_dev.part_type = PART_TYPE_DOS;
wdenk7205e402003-09-10 22:30:53 +0000435 mmc_dev.dev = 0;
436 mmc_dev.lun = 0;
437 mmc_dev.type = 0;
438 /* FIXME fill in the correct size (is set to 32MByte) */
439 mmc_dev.blksz = 512;
440 mmc_dev.lba = 0x10000;
441 sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
442 cid->id[0], cid->id[1], cid->id[2],
443 cid->sn[0], cid->sn[1], cid->sn[2]);
444 sprintf(mmc_dev.product,"%s",cid->name);
445 sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
446 mmc_dev.removable = 0;
447 mmc_dev.block_read = mmc_bread;
wdenk71f95112003-06-15 22:40:42 +0000448
449 /* MMC exists, get CSD too */
450 resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
451 resp = mmc_cmd(MMC_CMD_SEND_CSD, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R2);
wdenk20787e22005-04-06 00:04:16 +0000452 if (resp) {
wdenk71f95112003-06-15 22:40:42 +0000453 mmc_csd_t *csd = (mmc_csd_t *)resp;
454 memcpy(&mmc_csd, csd, sizeof(csd));
455 rc = 0;
456 mmc_ready = 1;
457 /* FIXME add verbose printout for csd */
458 }
459 }
460
wdenk20787e22005-04-06 00:04:16 +0000461#ifdef CONFIG_PXA27X
462 MMC_CLKRT = 1; /* 10 MHz - see Intel errata */
463#else
wdenk71f95112003-06-15 22:40:42 +0000464 MMC_CLKRT = 0; /* 20 MHz */
wdenk20787e22005-04-06 00:04:16 +0000465#endif
wdenk71f95112003-06-15 22:40:42 +0000466 resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
467
wdenk42d1f032003-10-15 23:53:47 +0000468 fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
wdenk71f95112003-06-15 22:40:42 +0000469
470 return rc;
471}
472
473int
474mmc_ident(block_dev_desc_t *dev)
475{
476 return 0;
477}
478
479int
480mmc2info(ulong addr)
481{
482 /* FIXME hard codes to 32 MB device */
wdenk20787e22005-04-06 00:04:16 +0000483 if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) {
wdenk71f95112003-06-15 22:40:42 +0000484 return 1;
485 }
486 return 0;
487}
488
wdenk20787e22005-04-06 00:04:16 +0000489#endif /* CONFIG_MMC */